John G Pellerin, 59Saratoga Springs, NY

6399493, Jun 4, 2002

May 17, 2001

09/860141

Robert Dawson - Austin TX
Jon D. Cheek - Round Rock TX
John G. Pellerin - Austin TX

Advanced Micro Devices, Inc. - Sunnyvale CA

H01L 2144

438682, 438683, 438586, 438592

Various methods of fabricating a silicide film and structures incorporating the same are provided. In one aspect, a method of fabricating a silicide film is provided that includes providing a silicon surface and etching the silicon surface at between isotropic and anisotropic etching conditions to define a plurality of oblique surfaces thereon and thereby increase the surface area of the silicon surface. A silicide-forming material is deposited on the plurality of oblique surfaces and the silicon surface is heated to react the silicide-forming material therewith and form silicide. The roughing of the silicon surface facilitates metal-silicide reactions.

6406964, Jun 18, 2002

Nov 1, 2000

09/704008

Derick J. Wristers - Austin TX
Jon D. Cheek - Round Rock TX
John G. Pellerin - Austin TX

Advanced Micro Devices, Inc. - Austin TX

H01L 21336

438305, 438303, 438308, 438571

The present invention is directed to a method of forming a transistor. In one embodiment, the method comprises providing a substrate, the substrate being doped with a first type of dopant material, forming a transistor above the substrate in an active area of the substrate as defined by an isolation structure, and performing at least one ion implant process to implant dopant atoms in the substrate adjacent the gate electrode of the transistor. The method further comprises performing at least two angled ion implant processes on the transistor with a dopant material that is of an opposite type to the first type of dopant material and performing at least one anneal process.

6580122, Jun 17, 2003

Mar 20, 2001

09/812521

Derick J. Wristers - Bee Caves TX
Jon D. Cheek - Round Rock TX
John G. Pellerin - Austin TX

Advanced Micro Devices, Inc. - Austin TX

H01L 2976

257330, 257332, 257374, 438270, 438259, 438589

The present invention is directed to a transistor having an enhanced width dimension and a method of making same. In one illustrative embodiment, the transistor comprises a semiconducting substrate, a recessed isolation structure formed in the substrate, the isolation structure defining a recess thereabove, a gate electrode and a gate insulation layer positioned above the substrate, a portion of the gate electrode and the gate insulation layer extending into the recess above the recessed isolation structure, and a source region and a drain region formed in the substrate. In another illustrative embodiment, the transistor comprises a semiconducting substrate, a recessed isolation structure that defines an active area having an upper surface and an exposed sidewall surface, a gate insulation layer and a gate electrode positioned above a portion of the upper surface and a portion of the exposed sidewall surface of the active area, and a source region and a drain region formed in the active area.

6713357, Mar 30, 2004

Dec 20, 2001

10/023348

Hai Hong Wang - Fremont CA
Mark W. Michael - Cedar Park TX
Wen-Jie Qi - Austin TX
William G. En - Milpitas CA
John G. Pellerin - Austin TX

Advanced Micro Devices, Inc. - Sunnyvale CA

H01L 21336

438287, 438230, 438696

The present invention relates to a method for fabricating MOS transistors with reduced parasitic capacitance. The present invention is based upon recognition that the parasitic capacitance of MOS transistors, such as are utilized in the manufacture of CMOS and IC devices, can be reduced by use of sidewall spacers having an optimized cross-sectional shape, in conjunction with an overlying insulator layer comprised of a low-k dielectric material.

6764917, Jul 20, 2004

Dec 20, 2001

10/023350

Darin A. Chan - Campbell CA
William G. En - Milpitas CA
John G. Pellerin - Austin TX
Mark W. Michael - Cedar Park TX

Advanced Micro Devices, Inc. - Sunnyvale CA

H01L 2176

438406, 438149, 438311, 438516

A method of manufacturing a semiconductor device includes providing a silicon semiconductor layer over an insulating layer, and partially removing a first portion of the silicon layer. The silicon layer includes the first portion and a second portion, and a thickness of the second portion is greater than a thickness of the first portion. Initially, the first and second portions of the silicon layer initially can have the same thickness. A semiconductor device is also disclosed.

6780776, Aug 24, 2004

Dec 20, 2001

10/023328

Wen-Jie Qi - Austin TX
John G. Pellerin - Austin TX
William G. En - Milpitas CA
Mark W. Michael - Cedar Park TX
Darin A. Chan - Campbell CA

Advanced Micro Devices, Inc. - Sunnyvale CA

H01L 21302

438706, 438710, 438712, 438720, 438745

A method of forming a semiconductor device provides a gate electrode on a substrate and forms a polysilicon reoxidation layer over the substrate and the gate electrode. A nitride layer is deposited over the polysilicon reoxidation layer and anisotropically etched The etching stops on the polysilicon reoxidation layer, with nitride offset spacers being formed on the gate electrode. The use of the polysilicon reoxidation layer as an etch stop layer prevents the gouging of the silicon substrate underneath the nitride layer, while allowing the offset spacers to be formed.

7074657, Jul 11, 2006

Nov 14, 2003

10/706948

James N. Pan - Fishkill NY, US
John G. Pellerin - Hopewell Junction NY, US
Jon Cheek - Wallkill NY, US

Advanced Micro Devices, Inc. - Sunnyvale CA

H01L 21/336

438193, 438300

A multiple-channel semiconductor device has fully or partially depleted quantum wells and is especially useful in ultra large scale integration devices, such as CMOSFETs. Multiple channel regions are provided on a substrate with a gate electrode formed on the uppermost channel region, separated by a gate oxide, for example. The vertical stacking of multiple channels and the gate electrode permit increased drive current in a semiconductor device without increasing the silicon area occupied by the device.

7091106, Aug 15, 2006

Mar 4, 2004

10/791759

Douglas J. Bonser - Hopewell Junction NY, US
Johannes F. Groschopf - Fishkill NY, US
John G. Pellerin - Hopewell Jct NY, US
Jon D. Cheek - Wallkill NY, US

Advanced Micro Devices, Inc. - Sunnyvale CA

H01L 21/76

438424, 257E21545, 257E21564

STI divot formation is eliminated or substantially reduced by employing a very thin nitride polish stop layer, e. g. , no thicker than 400 Å. The very thin nitride polish stop layer is retained in place during subsequent masking, implanting and cleaning steps to form dopant regions, and is removed prior to gate oxide and gate electrode formation.