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John J Vranich Deceased32 Cass St, Boston, MA 02132

Known as:
John M Vranich John J Vranch
Related to:
Susan Marie Vranich 64 Cynthia L Vranich 63

John Vranich Phones & Addresses

32 Cass St, West Roxbury, MA 02132    617-3250691   

Boston, MA   

203 Green Manor Rd, Enfield, CT 06082   

200 Massmills Dr, Lowell, MA 01852   

N Billerica, MA   

Los Angeles, CA   

Huntington Beach, CA   

N Billerica, MA   

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John J Vranich

Linkedin

Work

Position: Consultant

Education

Degree: Masters, Master of Science In Electrical Engineering School / High School: University of Southern California 1990 to 1991

Skills

Systemverilog • Rtl Design • Verilog • Embedded Systems • Asic • Soc • Debugging • Computer Architecture • Vhdl • Static Timing Analysis • Functional Verification • Modelsim • Digital Signal Processors • Fpga • Semiconductors • Ic • Eda • Hardware Architecture • Processors • Vlsi • Firmware • Application Specific Integrated Circuits • System on A Chip • Integrated Circuits

Languages

English

Interests

Football • Exercise • Home Improvement • Donor • Reading • Sports • Golf • Hockey • Watching Hockey • Home Decoration • Health • Watching Sports • Photograph • Cooking • Skiing • Electronics • Outdoors • Sewing • Baseball • Crafts • Fitness • Music • Camping • Dogs • Movies • Medicine • Joggin • Diet • Walking • Woodwork • Travel • Wine • Watching Baseball • Investing • Television • Watching Football

Industries

Computer Hardware
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Mentions for John J Vranich

John Vranich resumes & CV records

Resumes

John Vranich Photo 15

Consultant

Location:
32 Cass St, West Roxbury, MA 02132
Industry:
Computer Hardware
Work:

Consultant Intel Corporation Jun 2000 - May 2016
Architect and Senior Design Engineer Basis Communications Nov 1999 - Jun 2000
Engineer, Architect Picturetel 1995 - Nov 1999
Engineer, Manager Audio Dsp Group
Education:
University of Southern California 1990 - 1991
Masters, Master of Science In Electrical Engineering University of Pennsylvania 1981 - 1985
Bachelors, Bachelor of Science In Electrical Engineering
Skills:
Systemverilog, Rtl Design, Verilog, Embedded Systems, Asic, Soc, Debugging, Computer Architecture, Vhdl, Static Timing Analysis, Functional Verification, Modelsim, Digital Signal Processors, Fpga, Semiconductors, Ic, Eda, Hardware Architecture, Processors, Vlsi, Firmware, Application Specific Integrated Circuits, System on A Chip, Integrated Circuits
Interests:
Football
Exercise
Home Improvement
Donor
Reading
Sports
Golf
Hockey
Watching Hockey
Home Decoration
Health
Watching Sports
Photograph
Cooking
Skiing
Electronics
Outdoors
Sewing
Baseball
Crafts
Fitness
Music
Camping
Dogs
Movies
Medicine
Joggin
Diet
Walking
Woodwork
Travel
Wine
Watching Baseball
Investing
Television
Watching Football
Languages:
English

Publications & IP owners

Us Patents

High Performance Raid-6 System Architecture With Pattern Matching

US Patent:
2008014, Jun 19, 2008
Filed:
Dec 19, 2006
Appl. No.:
11/642315
Inventors:
Vinodh Gopal - Westboro MA, US
Gilbert Wolrich - Framingham MA, US
Kirk S. Yap - Framingham MA, US
Wajdi K. Feghali - Boston MA, US
John Vranich - West Roxbury MA, US
Robert P. Ottavi - Brookline NH, US
International Classification:
G06F 7/44
US Classification:
712225
Abstract:
An acceleration unit offloads computationally intensive tasks from a processor. The acceleration unit includes two data processing paths each having an Arithmetic Logical Unit and sharing a single multiplier unit. Each data processing path may perform configurable operations in parallel on a same data. Special multiplexer paths and instructions are provided to allow P and Q type syndromes to be computed on a stripe in a single-pass of the data through the acceleration unit.

Method And Apparatus For Testing Mathematical Algorithms

US Patent:
2009008, Apr 2, 2009
Filed:
Sep 28, 2007
Appl. No.:
11/864896
Inventors:
Vinodh Gopal - Westboro MA, US
John Vranich - West Roxbury MA, US
Pierre Laurent - Quin County Clare, IE
Daniel Cutter - Maynard MA, US
Wajdi K. Feghali - Boston MA, US
Andrew Milne - Ottawa, CA
Erdinc Ozturk - Worcester MA, US
International Classification:
G06F 11/07
US Classification:
714 32, 714E11021
Abstract:
A method and apparatus for testing mathematical programs where code coverage is exceedingly difficult to hit with random data test vectors (probability

Method And Apparatus For Managing Serial Peripheral Interface (Spi) Flash

US Patent:
2014029, Oct 2, 2014
Filed:
Mar 29, 2013
Appl. No.:
13/853429
Inventors:
Nitin V. Sarangdhar - Portland OR, US
John J. Vranich - West Roxbury MA, US
Kirk D. Brannock - Hillsboro OR, US
Steven Dennison - Folsom CA, US
International Classification:
G06F 12/02
US Classification:
711103
Abstract:
A system for communicating with a flash device includes: a controller configured for communicating with the flash device, the controller including logic for classifying a command to the flash device as one of safe and unsafe and communicating each safe command. Methods and a computer program product and a computing system are disclosed.

Secure Replay Protected Storage

US Patent:
2014022, Aug 7, 2014
Filed:
Dec 20, 2011
Appl. No.:
13/997896
Inventors:
John J. Vranich - West Roxbury MA, US
International Classification:
G06F 12/14
US Classification:
713193
Abstract:
Embodiments of the invention create an underlying infrastructure in a flash memory device (e.g., a serial peripheral interface (SPI) flash memory device) such that it may be protected against user attacks—e.g., replacing the SPI flash memory device or a man-in-the-middle (MITM) attack to modify the SPI flash memory contents on the fly. In the prior art, monotonic counters cannot be stored in SPI flash memory devices because said devices do not provide replay protection for the counters. A user may also remove the flash memory device and reprogram it. Host platforms alone cannot protect against such hardware attacks.Embodiments of the invention enable secure standard storage flash memory devices such as SPI flash memory devices to achieve replay protection for securely stored data. Embodiments of the invention utilize flash memory controllers, flash memory devices, unique device keys and HMAC key logic to create secure execution environments for various components.

Possible Relatives

James K Vranich  Joseph Vranich  Mark R Vranich  Thomas M Vranich  John M Johnson  John Stamps  John R Stan  John Stanard  John R Stanaway  John R Stanbery 

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