BackgroundCheck.run
Search For

John M Weinerth, 401290 Chilanian Ln, San Jose, CA 95120

Known as:
John B Weinerth John M Weinert John M Welnert John H
Related to:
John M Weinert 40

John Weinerth Phones & Addresses

San Jose, CA   

Carmel Valley, CA   

Bradley, CA   

1290 Chilanian Ln, San Jose, CA 95120   

Get Report
Control this profile

Mentions for John M Weinerth

Career records & work history

Medicine Doctors

John Weinerth Photo 1

John Louis Weinerth

Specialties:
Urology
Surgery
Education:
Harvard University(1967)

John Weinerth resumes & CV records

Resumes

John Weinerth Photo 9

Analog Design Engineer

Location:
Berkeley, CA
Industry:
Design
Work:
Synaptics
Analog Design Engineer Synaptics Jun 2008 - Jul 2009
Analog Verification Engineer Synaptics May 2007 - May 2008
Asic Design Intern Novellus Systems Jun 2006 - May 2007
Electrical Engineering Intern
Education:
University of California, Los Angeles 2008 - 2011
Masters, Master of Science In Electrical Engineering San Jose State University 2003 - 2008
Bachelors, Bachelor of Science, Electronics Engineering
Skills:
Asic, Analog Circuit Design, Analog, Labview, Verilog, Electrical Engineering, Matlab, Semiconductors, C, Circuit Design, Microcontrollers, Debugging, Embedded Systems, Digital Signal Processors, Eda, Ic, Vhdl, Modelsim, Integrated Circuit Design, Pcb Design, Fpga, Vlsi, Hardware Architecture, Cadence Virtuoso, Mixed Signal
John Weinerth Photo 10

John Weinerth

Publications & IP owners

Us Patents

System And Method For Determining User Input And Interference On An Input Device

US Patent:
2012022, Sep 13, 2012
Filed:
Mar 8, 2011
Appl. No.:
13/043250
Inventors:
Adam Schwartz - Redwood City CA, US
Joseph Kurth Reynolds - Mountain View CA, US
John Weinerth - San Jose CA, US
Joel C. Jordan - Sunnyvale CA, US
Assignee:
SYNAPTICS INCORPORATED - Santa Clara CA
International Classification:
G06F 3/044
US Classification:
345174
Abstract:
The embodiments described herein provide devices and methods that facilitate improved performance. In one embodiment, an input device comprises a processing system, a transmitter sensor electrode, and a receiver sensor electrode, where the transmitter sensor electrode and the receiver sensor electrode are capacitively coupled. The processing system is configured to receive a resulting signal from the receiver sensor electrode, where the resulting signal includes responses that correspond to the transmitter signal. The processing system is further configured to separately accumulate, for each cycle of the transmitter waveform, a first portion and a second portion of the resulting signal to respectively produce a first accumulation and a second accumulation, wherein the first accumulation is used for determining user input to the input device and the second accumulation is used for determining interference, and wherein the first portion and the second portion are non-coterminous.

Input Device Receiver Path And Transmitter Path Error Diagnosis

US Patent:
2012020, Aug 16, 2012
Filed:
Feb 16, 2011
Appl. No.:
13/028876
Inventors:
John Weinerth - San Jose CA, US
Shahrooz Shahparnia - Campbell CA, US
Vivek Pant - San Jose CA, US
Joseph Kurth Reynolds - Alviso CA, US
International Classification:
H04L 27/00
US Classification:
375316
Abstract:
An input device comprises a processing system coupled with a plurality of receiver paths. The processing system comprises a first capacitor and a bypass switch. The first capacitor is configured to be selectively coupled with the plurality of receiver paths. The bypass switch is configured for bypassing the first capacitor. The processing system is configured to selectively couple a first receiver path of the plurality of receiver paths with the first capacitor; acquire a measurement of a first resulting signal from at least one of the first receiver path or a second receiver path of the plurality of receiver paths while the first receiver path is coupled with the first capacitor and while the bypass switch is not bypassing the first capacitor; and determine whether the first receiver path is ohmically coupled with the second receiver path based on the measurement of the first resulting signal.

Capacitive Sensing Acquisition Schemes

US Patent:
2020037, Dec 3, 2020
Filed:
Aug 14, 2020
Appl. No.:
16/994460
Inventors:
- San Jose CA, US
John Weinerth - San Jose CA, US
Derek Solven - San Jose CA, US
David Hoch - San Jose CA, US
Assignee:
Synaptics Incorporated - San Jose CA
International Classification:
G06F 3/044
G06F 3/041
Abstract:
An input device including a sensing region is disclosed. The input device includes: sensor circuitry configured to: operate, during a first timeslot, electrodes as a first cluster; and operate, during a second timeslot, the electrodes as a second cluster, where the electrodes are aligned with an axis, and where at least one of the electrodes operates as a transmitter in the first cluster and as a receiver in the second cluster; and determination circuitry configured to: determine a first set of signal values associated with a first set of electrodes in the first cluster; determine a second set of signal values associated with a second set of electrodes in the second cluster; and generate a profile for the sensing region based on the first set of signal values and the second set of signal values, where the profile reflects an input object in the sensing region.

Method And System For Alternative Absolute Profile Determination

US Patent:
2020036, Nov 19, 2020
Filed:
Jul 30, 2020
Appl. No.:
16/943754
Inventors:
- San Jose CA, US
John Weinerth - San Jose CA, US
Assignee:
Synaptics Incorporated - San Jose CA
International Classification:
G06F 3/041
G06F 3/044
Abstract:
The invention relates to a processing system. The processing system includes a sensor module performing a first measurement to obtain a combination signal using a first sensor electrode and a second sensor electrode. The first electrode is driven using a first modulated signal with a first driving voltage amplitude and simultaneously the second electrode is driven using a second modulated signal with a second driving voltage amplitude greater than the first driving voltage amplitude, while simultaneously first and second resulting signals are received from the first and second electrodes, respectively. The sensor module is further performs a second measurement to obtain a transcapacitance signal using the first and second sensor electrodes. The processing system also includes a determination module that generates the combination signal by combining the first and second resulting signals, and computes an absolute capacitance signal from the combination signal, the transcapacitance signal, and a background capacitance.

Capacitive Sensing Acquisition Schemes

US Patent:
2020020, Jun 25, 2020
Filed:
Dec 19, 2018
Appl. No.:
16/226123
Inventors:
- San Jose CA, US
John Weinerth - San Jose CA, US
Derek Solven - San Jose CA, US
David Hoch - San Jose CA, US
International Classification:
G06F 3/044
G06F 3/041
Abstract:
An input device including a sensing region is disclosed. The input device includes: sensor circuitry configured to: operate, during a first timeslot, electrodes as a first cluster; and operate, during a second timeslot, the electrodes as a second cluster, where the electrodes are aligned with an axis, and where at least one of the electrodes operates as a transmitter in the first cluster and as a receiver in the second cluster; and determination circuitry configured to: determine a first set of signal values associated with a first set of electrodes in the first cluster; determine a second set of signal values associated with a second set of electrodes in the second cluster; and generate a profile for the sensing region based on the first set of signal values and the second set of signal values, where the profile reflects an input object in the sensing region.

Transmitter Axis Projection Construction For Capacitive Sensing

US Patent:
2019005, Feb 21, 2019
Filed:
Aug 21, 2017
Appl. No.:
15/682284
Inventors:
- San Jose CA, US
John Weinerth - San Jose CA, US
Jonathan Losh - San Jose CA, US
Derek Solven - San Jose CA, US
International Classification:
G06F 3/044
G01R 27/26
G06F 3/041
Abstract:
Transmitter axis projection for capacitive sensing is disclosed. Transmitter axis projection includes having processing system. The processing system includes sensor circuitry configured to be coupled to transmitter electrodes and receiver electrodes. The sensor circuitry is configured to drive the transmitter electrodes with first transmitter signals and receive first resulting signals from the receiver electrodes, and drive only a first subset of the receiver electrodes with second transmitter signals and receive second resulting signals with the transmitter electrodes. The processing system further includes processing circuitry connected to the sensor circuitry and configured to partition the receiver electrodes into the first subset of receiver electrodes and a second subset of receiver electrodes, and generate a transmitter axis projection from the second resulting signals.

Method And System For Alternative Absolute Profile Determination

US Patent:
2019005, Feb 21, 2019
Filed:
Jun 20, 2018
Appl. No.:
16/013694
Inventors:
- San Jose CA, US
John Weinerth - San Jose CA, US
International Classification:
G06F 3/044
G06F 3/041
Abstract:
The invention relates to a processing system. The processing system includes a sensor module performing a first measurement to obtain a combination signal using a first sensor electrode and a second sensor electrode. The first electrode is driven using a first modulated signal with a first driving voltage amplitude and simultaneously the second electrode is driven using a second modulated signal with a second driving voltage amplitude greater than the first driving voltage amplitude, while simultaneously first and second resulting signals are received from the first and second electrodes, respectively. The sensor module is further performs a second measurement to obtain a transcapacitance signal using the first and second sensor electrodes. The processing system also includes a determination module that generates the combination signal by combining the first and second resulting signals, and computes an absolute capacitance signal from the combination signal, the transcapacitance signal, and a background capacitance.

Reducing Background Capacitance Associated With A Touch Surface

US Patent:
2018014, May 24, 2018
Filed:
Nov 18, 2016
Appl. No.:
15/355308
Inventors:
- San Jose CA, US
John Weinerth - San Jose CA, US
Derek Solven - San Jose CA, US
International Classification:
G06F 3/041
G06F 3/044
Abstract:
A processing system for reducing background capacitance associated with a touch surface. The processing system includes: transmitter circuitry that drives a transmitter electrode of the touch surface with a waveform; receiver circuitry that detects input in a sensing region of the touch surface based on a resulting signal from a receiver electrode of the touch surface; and offset reduction circuitry connected to the receiver circuitry that: subtracts, prior to completion of an integration period of the waveform, a first plurality of charge associated with background capacitance from the resulting signal using a capacitor; executes a first reload of the capacitor prior to completion of the integration period of the waveform; and subtracts, prior to completion of the integration period of the waveform, a second plurality of charge associated with background capacitance from the resulting signal using the capacitor after the first reload.

Possible Relatives

John M Johnson  John Stamps  John R Stan  John Stanard  John R Stanaway  John R Stanbery  John L Stanbrough  John C Stanchak  John Stanchek  John C Stancil 

NOTICE: You may not use BackgroundCheck or the information it provides to make decisions about employment, credit, housing or any other purpose that would require Fair Credit Reporting Act (FCRA) compliance. BackgroundCheck is not a Consumer Reporting Agency (CRA) as defined by the FCRA and does not provide consumer reports.