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Jon Alan Gwin, 632913 Silver Fountain Dr, Leander, TX 78641

Known as:
Jon A Gwin Jan A Gwin Jana Gwin Jon Gwen
Related to:
Joyce S Gwinn 78

Jon Gwin Phones & Addresses

2913 Silver Fountain Dr, Leander, TX 78641    512-8284946   

Austin, TX   

3114 Knight Robin Dr, San Antonio, TX 78209   

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Resumes

Jon Gwin Photo 25

General Manager

Location:
Austin, TX
Industry:
Sports
Work:
Nitro Swimming
General Manager Silicon Space Technology Feb 2004 - Jan 2013
Co-Founder and Vice President Sony Semiconductor of America Jun 1998 - Oct 2003
Foundry Services Account Manager Sony Semiconductor of America Sep 1988 - Jun 1998
Staff Engineer and Department Manager
Education:
The University of Texas at San Antonio 1995 - 1997
Master of Science, Masters, Management Florida Institute of Technology 1979 - 1983
Bachelors, Bachelor of Science, Chemical Engineering
Skills:
Team Leadership, Strategic Planning, Contract Negotiation, Start Ups, Program Management, Semiconductors, Customer Service, Executive Management, Cross Functional Collaborations, Negotiation, Problem Solving, Corporate Governance, Project Management, Swimming, Operations Management, Contract Management, Foundry Management, Patents, Trademarks
Jon Gwin Photo 26

Jon Gwin

Publications & IP owners

Us Patents

Radiation Immunity Of Integrated Circuits Using Backside Die Contact And Electrically Conductive Layers

US Patent:
2008014, Jun 19, 2008
Filed:
Aug 4, 2007
Appl. No.:
11/833989
Inventors:
Wesley H. Morris - Austin TX, US
Jon Gwin - San Antonio TX, US
Rex Lowther - Palm Bay FL, US
Assignee:
SILICON SPACE TECHNOLOGY CORPORATION - Austin TX
International Classification:
H01L 29/36
H01L 21/223
US Classification:
257371, 438526, 257369, 257E29109, 257E21143
Abstract:
Radiation hardened integrated circuit devices may be fabricated using conventional designs and process, but including specialized structures to reduce or eliminate detrimental effects caused by various forms of radiation. An exemplary BGR structure includes a high-dose buried guard ring (HBGR) layer which is contacted to ground through the backside of the wafer or circuit die, thus forming a Backside BGR (BBGR) structure. In certain embodiments, the starting wafer may be highly doped to reduce the resistance from the HBGR to the back of the wafer, which is then further contacted to ground through the package. The performance of such devices may be further improved by using an electrically conductive adhesive to attach the die and to electrically connect the silicon substrate region to the package's conductive header, substrate, or die attach pad, which in turn is typically connected to one or more package pins/balls.

Apparatus For Weighting A Diffusion Furnace Cantilever

US Patent:
5372649, Dec 13, 1994
Filed:
Aug 30, 1993
Appl. No.:
8/113521
Inventors:
Jon A. Gwin - San Antonio TX
Assignee:
Sony Electronics, Inc. - Park Ridge NJ
International Classification:
B05C 1302
US Classification:
118728
Abstract:
Apparatus for counterweighting a diffusion furnace cantilever arm for processing silicon wafers which has conventional slotted quartz boats for receiving silicon wafers wherein certain substitutes for said conventional quartz boats are constructed so as to be dummy loads which have the weight and dimensions of a filled quartz boat, but in which no silicon wafers are mounted. Other quartz boats have slots for a particular number of silicon wafers, but the remaining portion of the boat does not receive any wafers, and the boat has the weight and dimensions equivalent to a filled quartz boat. By combining the various boats on the cantilever arm a standard weight can be obtained.

Etching Tool

US Patent:
5429704, Jul 4, 1995
Filed:
Nov 16, 1993
Appl. No.:
8/153404
Inventors:
Charles A. Butler - San Antonio TX
Jon Gwin - San Antonio TX
Assignee:
Sony Electronics, Inc.
International Classification:
C23F 102
US Classification:
156345
Abstract:
A tool for etching at least one selected area of a silicon dixoide layer on a wafer. The tool includes a container which is partially filled with hydrofluoric (HF) acid. The tool further includes a template having an aperture extending between each selected area and the container. Vapors of the HF acid pass through each aperture to contact and etch each selected area in order to expose a test die on the wafer. An O-ring is associated with each selected area for sealing each of the selected areas from the remaining areas on the silicon dioxide layer such that substantially only the selected areas are etched by the vapors.

High Capacity Semiconductor Dopant Deposition/Oxidization Process Using A Single Furnace Cycle

US Patent:
5494852, Feb 27, 1996
Filed:
Jul 28, 1993
Appl. No.:
8/098667
Inventors:
Jon A. Gwin - San Antonio TX
Assignee:
Sony Electronics Inc. - Park Ridge NJ
International Classification:
H01L 21225
H01L 21385
US Classification:
437164
Abstract:
A semiconductor deposition and oxidation process using a single furnace cycle. The temperature and gas mixture is stabilized inside the furnace prior to introduction of a dopant at a relatively low temperature. The temperature of the chamber is then ramped-up and the dopant is diffused into the wafer in an inert ambient. The temperature is then ramped-up again and oxygen is introduced to produce an oxide layer. The wafers are then removed from the furnace and any residue of the dopant within the chamber is effectively neutralized by introducing a high flow of oxygen.

Semiconductor Device Produced By A Single Furnace Cycle Diffusion And Oxidation Process

US Patent:
5786605, Jul 28, 1998
Filed:
Aug 6, 1997
Appl. No.:
8/907264
Inventors:
Jon A. Gwin - San Antonio TX
Assignee:
Sony Corporation - Tokyo
Sony Electronics Inc - Park Ridge NJ
International Classification:
H01L 21225
US Classification:
257101
Abstract:
A semiconductor deposition and oxidation process using a single furnace cycle. The temperature and gas mixture is stabilized inside the furnace prior to introduction of a dopant at a relatively low temperature. The temperature of the chamber is then ramped-up and the dopant is diffused into the wafer in an inert ambient. The temperature is then ramped-up again and oxygen is introduced to produce an oxide layer. The wafers are then removed from the furnace and any residue of the dopant within the chamber is effectively neutralized by introducing a high flow of oxygen.

Possible Relatives

Cynthia L Gwin  David M Gwin  Dawn M Gwin  Deborah D Gwin  Dana R Gwin  Debra Gwin  Danny L Gwin  Jon A Johnson  Jon A Standerfer  Jon D Standridge 

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