John S Walters, 651022 Wilbrook, Palmer, TX 75152

6354092, Mar 12, 2002

Aug 21, 2000

09/641950

Michael Raymond Young - York PA
Gordon Ted Boyd - Knoxville TN
John Richard Walters - Abingdon VA
Scott Garrison Hix - Bristol VA

York International Corporation - DE

F25B 4300

62 83, 62217, 62503

A liquid arresting valve for a refrigeration compressor having a refrigerant intake, including a housing having an inlet end to receive liquid and vapor phase refrigerant from an evaporator and an outlet end for connection to the refrigerant intake of the compressor, and a valve body movable in the housing between an open position permitting substantially unrestricted flow of vapor phase refrigerant between the inlet and outlet ends of the housing, and a flow restricting position to cause liquid containing refrigerant entering the inlet end of the housing to exit through the outlet end of the housing as vapor phase refrigerant.

7108403, Sep 19, 2006

Apr 12, 2004

10/822238

John Walters - Mechanicsburg PA, US
Tina R. Walters - Mechanicsburg PA, US

B60Q 1/00
H01R 33/00

362368, 362652, 362640, 362800

A portable light emitting assembly includes a housing having a front side, a back side and a peripheral wall extending between the front and back sides. The front side has a cavity extending therein. A panel has a first side and a second side. The panel is removably mounted in the cavity. A plurality of light emitters is attached to the second side of the panel. A first electrical conduit is mounted on the back wall and a second electrical conduit is mounted on the first side of the panel. The first electrical conduit is positioned for electrically coupling with the second electrical conduit when the panel is positioned within the cavity. The second electrical conduit is electrically coupled to the light emitters. A power supply is mounted within the housing. The power supply is electrically coupled to the first electrical conduit.

5478771, Dec 26, 1995

Dec 19, 1994

8/359006

Tsiu C. Chan - Carrollton TX
Frank R. Bryant - Denton TX
John L. Walters - Carrollton TX

SGS-Thomson Microelectronics, Inc. - Carrollton TX

H01L 2170

437 57

An interconnect structure, and method for forming same, is suitable for use in integrated circuits such as SRAM devices. The structure uses masking of a polycrystalline silicon interconnect level to move a P-N junction to a region within a polycrystalline silicon interconnect line, rather than at the substrate. This P-N junction can then be shorted out using a refractory metal silicide formed on the polycrystalline silicon interconnect structure.

5065225, Nov 12, 1991

Jul 31, 1990

7/560384

Frank R. Bryant - Denton TX
John L. Walters - Carrollton TX

SGS-Thomson Microelectronics, Inc. - Carrollton TX

H01L 2348
H01L 4902
H01L 2702
H01L 2904

357 71

A semiconductor device is described in which a conductive layer overlaps a dielectric layer forming a composite electrical device deposited over selected portions of a semiconductor substrate chemically isolating the conductive layer portion of the composite electrical device from the substrate, thereby preventing difffusion of dopant material through the dielectric layer into and out of the conductive layer while simultaneously allowing for tunneling of electrons through the dielectric layer to and from the conductive layer and the semiconductor substrate.

5841195, Nov 24, 1998

May 24, 1995

8/448703

Lun-Tseng Lu - Grand Praire TX
Fu-Tai Liou - Carrollton TX
Che-Chia Wei - Plano TX
John Leonard Walters - Carrollton TX

STMicroelectronics, Inc. - Carrollton TX

H01L 23532

257774

A method is provided for forming contact via in an integrated circuit. Initially, a first buffer layer is formed over an insulating layer in an integrated circuit. The first buffer layer has a different etch rate from the insulating layer. A second buffer layer is then formed over the first buffer layer, with the second buffer layer having an etch rate which is faster than the first buffer layer. An isotropic etch is performed to create an opening through the second buffer layer and a portion of the first buffer layer. Because the second buffer layer etches faster than the first buffer layer, the slant of the sideswalls of the opening can be controlled. An anisotropic etch is then performed to complete formation of the contact via.

5246883, Sep 21, 1993

Feb 6, 1992

7/832088

Lun-Tseng Lu - Grand Prairie TX
Fu-Tai Liou - Carrollton TX
Che-Chia Wei - Plano TX
John L. Walters - Carrollton TX

SGS-Thomson Microelectronics, Inc. - Carrollton TX

H01L 21302

437195

A method is provided for forming contact vias in an integrated circuit. Initially, a first buffer layer is formed over an insulating layer in an integrated circuit. The first buffer layer has a different etch rate from the insulating layer. A second buffer layer is then formed over the first buffer layer, with the second buffer layer having an etch rate which is faster than the first buffer layer. An isotropic etch is performed to create an opening through the second buffer layer and a portion of the first buffer layer. Because the second buffer layer etches faster than the first buffer layer, the slant of the sideswalls of the opening can be controlled. An anisotropic etch is then performed to complete formation of the contact via.

5670424, Sep 23, 1997

Oct 13, 1995

8/542815

Tsiu Chiu Chan - Carrollton TX
Frank Randolph Bryant - Denton TX
John Leonard Walters - Carrollton TX

SGS-Thomson Microelectronics, Inc. - Carrollton TX

H01L 2144

437193

An interconnect structure, and method for forming same, is suitable for use in integrated circuits such as SRAM devices. The structure uses masking of a polycrystalline silicon interconnect level to move a P-N junction to a region within a polycrystalline silicon interconnect line, rather than at the substrate. This P-N junction can then be shorted out using a refractory metal silicide formed on the polycrystalline silicon interconnect structure.

5489797, Feb 6, 1996

Apr 11, 1995

8/420353

Tsiu C. Chan - Carollton TX
Frank R. Bryant - Denton TX
John L. Walters - Carrollton TX

SGS-Thomson Microelectronics, Inc. - Carrollton TX

H01L 2976
H01L 2994
H01L 2711

257382

An interconnect structure, and method for forming same, is suitable for use in integrated circuits such as SRAM devices. The structure uses masking of a polycrystalline silicon interconnect level to move a P-N junction to a region within a polycrystalline silicon interconnect line, rather than at the substrate. This P-N junction can then be shorted out using a refractory metal silicide formed on the polycrystalline silicon interconnect structure.