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Jonathan Marion Douglas, 4196 W Lewis Ave, Phoenix, AZ 85003

Jonathan Douglas Phones & Addresses

96 W Lewis Ave, Phoenix, AZ 85003   

Tempe, AZ   

Grand Rapids, MI   

Scottsdale, AZ   

Chicago, IL   

2515 Leonard St NW, Grand Rapids, MI 49504   

Mentions for Jonathan Marion Douglas

Career records & work history

Lawyers & Attorneys

Jonathan Douglas Photo 1

Jonathan Douglas - Lawyer

Office:
Nabarro LLP
ISLN:
920403998
Jonathan Douglas Photo 2

Jonathan Douglas - Lawyer

ISLN:
1000537134
Admitted:
1979

License Records

Jonathan T Douglas

Licenses:
License #: 35456 - Active
Category: Tow Truck Operator (Consent Tow)
Expiration Date: Nov 2, 2017

Jonathan Douglas resumes & CV records

Resumes

Jonathan Douglas Photo 44

3D / 2D / Fx Artist

Location:
United States
Industry:
Graphic Design
Work:
Archasis Mod - Austin, Texas Area Oct 2008 - Dec 2008
3D Prop Artist
Education:
Austin Community College 2008 - 2011
Videogame Art Specialization
Texas State Technical College 2004 - 2007
Associate, Digital Media Design
Skills:
Digital Art, 3D Modeling, Texturing, Animation, Graphic Design, Video Editing, Audio Editing, Photo Manipulation, Gameplay, Hardcore Gamer
Interests:
Videogames, Art
Jonathan Douglas Photo 45

Jonathan Douglas

Work:
Noble Drilling 2012 - 2014
Rig Mechanic
Jonathan Douglas Photo 46

Jonathan Douglas

Jonathan Douglas Photo 47

Jonathan Douglas

Jonathan Douglas Photo 48

Web Developer

Work:

Web Developer
Jonathan Douglas Photo 49

Jonathan Douglas

Jonathan Douglas Photo 50

Acount Advisor At Unitedhealth Group

Location:
United States
Industry:
Hospital & Health Care
Jonathan Douglas Photo 51

Jonathan Douglas - Springfield, MO

Work:
ASSOCIATED ELECTRIC COOPERATIVE, INC Nov 2005 to 2000
SYSTEMS ADMINISTRATION SUPERVISOR/LEAD ARCHITECT
Douglas, J - Phoenix, AZ 2010 to 2010 ISG TECHNOLOGY, INC Oct 2004 to Nov 2005
SENIOR SYSTEMS ENGINEER
DRURY UNIVERSITY Nov 2000 to Feb 2004
SYSTEMS ADMINISTRATOR, TECHNOLOGY SERVICES
Education:
University of Phoenix - Phoenix, AZ 2010
Doctor of Management in Organizational Leadership
University of Phoenix - Phoenix, AZ 2004
MS in Computer Information Systems
Northern Michigan University - Marquette, MI 2000
BS in Computer Information Systems
Southwest Baptist University - Bolivar, MO 1998 to 1999
BS
Mineral Area College - Park Hills, MO 1998
AA in Computer Science

Publications & IP owners

Us Patents

Device, Method And System To Determine A Mode Of Voltage Regulation Based On Parasitics Of A Power Delivery Network

US Patent:
2022041, Dec 29, 2022
Filed:
Jun 25, 2021
Appl. No.:
17/359413
Inventors:
- Santa Clara CA, US
Mauricio Aguilar Salas - Heredia, CR
Jonathan Douglas - Cave Creek AZ, US
Anant Deval - Portland OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G05F 1/59
G06F 1/3203
G05F 1/575
Abstract:
Techniques and mechanisms for determining an operational mode of a voltage regulator. In an embodiment, an integrated circuit (IC) die is coupled to receive power from a voltage regulator (VR) via a power delivery network (PDN) which comprises circuitry in or on a substrate, such as that of a printed circuit board. The IC die receives from the substrate information indicating a characteristic of a parasitic impedance at the substrate. Based on the information, a controller unit at the IC die selects one of multiple VR modes which each correspond to a respective one of different parasitic impedance characteristics. The controller then signals the VR to provide the selected mode. In an embodiment one of the VR modes corresponds to a relatively high impedance, and also corresponds to a relatively stable sensitivity function in a frequency range above a control bandwidth.

Apparatus And Method To Reduce Power Losses In An Integrated Voltage Regulator

US Patent:
2018010, Apr 12, 2018
Filed:
Sep 5, 2017
Appl. No.:
15/695947
Inventors:
- Santa Clara CA, US
Srikrishnan Venkataraman - Bangalore, IN
William J. Lambert - Chandler AZ, US
Michael J. Hill - Gilbert AZ, US
Alexander Slepoy - Chandler AZ, US
Dong Zhong - Chandler AZ, US
Kaladhar Radhakrishnan - Gilbert AZ, US
Hector A. Aguirre Diaz - Guadalaraja, MX
Jonathan P. Douglas - Portland OR, US
International Classification:
G06F 1/26
Abstract:
Described is an apparatus which comprises: a first voltage regulator (VR) coupled to first one or more inductors, the first VR is to provide power to a first power domain; and a second VR coupled to second one or more inductors at least one of which is inductively coupled to at least one of the first one or more inductors, the second VR is to provide power to a second power domain separate from the first power domain, wherein there is a non-zero phase angle offset between switching transistors of the first VR relative to the second VR.

Apparatus And Method To Reduce Power Losses In An Integrated Voltage Regulator

US Patent:
2017006, Mar 2, 2017
Filed:
Aug 26, 2015
Appl. No.:
14/836780
Inventors:
- Santa Clara CA, US
Srikrishnan Venkataraman - Bangalore, IN
William J. Lambert - Chandler AZ, US
Michael J. Hill - Gilbert AZ, US
Alexander Slepoy - Chandler AZ, US
Dong Zhong - Chandler AZ, US
Kaladhar Radhakrishnan - Gilbert AZ, US
Hector A. Aguirre Diaz - Guadalaraja, MX
Jonathan P. Douglas - Portland OR, US
International Classification:
G06F 1/26
H02J 1/00
G06F 1/32
H02M 3/158
Abstract:
Described is an apparatus which comprises: a first voltage regulator (VR) coupled to first one or more inductors, the first VR is to provide power to a first power domain; and a second VR coupled to second one or more inductors at least one of which is inductively coupled to at least one of the first one or more inductors, the second VR is to provide power to a second power domain separate from the first power domain, wherein there is a non-zero phase angle offset between switching transistors of the first VR relative to the second VR.

Isbn (Books And Publications)

Butterflies Of The Great Lakes Region

Author:
Jonathan M. Douglas
ISBN #:
0472068849

Butterflies Of The Great Lakes Region

Author:
Jonathan M. Douglas
ISBN #:
0472098845

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