Jonathan B Sweedler, 5914569 Clearview Dr, Los Gatos, CA 95032

7398356, Jul 8, 2008

Jul 13, 2005

11/181117

Hoai V. Tran - Gilroy CA, US
Kevin Jerome Rowett - Cupertino CA, US
Somsubhra Sikdar - San Jose CA, US
Jonathan Sweedler - Los Gatos CA, US
Caveh Jalali - Redwood City CA, US

Mistletoe Technologies, Inc. - Cupertino CA

G06F 12/00

711119, 711122

A memory subsystem includes multiple different caches configured for different types of data transfer operations between one or more processing units and a main memory. The different caches can include a first general cache configured for general random memory accesses, a software controlled cache used for controlling cache operations for different processing devices accessing the same data, and a streaming cache configured for large packet data memory accesses. An arbiter may be used for arbitrating requests by the multiple different caches for accessing the main memory.

7424571, Sep 9, 2008

Jul 13, 2005

11/181611

Somsubhra Sikdar - San Jose CA, US
Kevin Jerome Rowett - Cupertino CA, US
Hoai V. Tran - Gilroy CA, US
Jonathan Sweedler - Los Gatos CA, US
Komal Rathi - Sunnyvale CA, US
Mike Davoudi - San Jose CA, US

Gigafin Networks, Inc. - Cupertino CA

G06F 12/02

711108, 711101, 710 52, 710 56

A device performs lookup functions for a semantic processing unit. The device comprises a plurality of interface circuits for receiving data operation requests from the semantic processing unit. The device comprises a buffer for allocating an interface circuit to a semantic processing unit having a data operation request. A selection circuit, coupled between the plurality of interface circuits and a memory unit, selects an allocated circuit for accessing the memory unit to process the data operation request.

7451268, Nov 11, 2008

Jul 13, 2005

11/181598

Somsubhra Sikdar - San Jose CA, US
Kevin Jerome Rowett - Cupertino CA, US
Hoai V. Tran - Gilroy CA, US
Jonathan Sweedler - Los Gatos CA, US
Komal Rathi - Sunnyvale CA, US
Mike Davoudi - San Jose CA, US

Gigafin Networks, Inc. - Cupertino CA

G06F 12/02

711108, 710 52, 710 56

A device comprises a plurality of interface circuits configured for communicating between a semantic processing unit and a memory and a selection circuit for selecting an interface circuit allocated to a semantic processing unit for processing a data operation request in the memory.

2006002, Feb 2, 2006

Jul 13, 2005

11/181599

Somsubhra Sikdar - San Jose CA, US
Kevin Rowett - Cupertino CA, US
Hoai Tran - Gilroy CA, US
Jonathan Sweedler - Los Gatos CA, US
Komal Rathi - Sunnyvale CA, US
Mike Davoudi - San Jose CA, US

G06F 12/00

711170000, 711118000

A device comprises a plurality of interface circuits for communicating between a semantic processor and a memory. Each interface circuit is configured for receiving lookup requests from the semantic processor. The device further comprises a buffer for allocating an interface circuit, if available, to the semantic processor. The allocated interface circuit is selected to access the memory for processing the lookup request.

2007001, Jan 18, 2007

Jul 18, 2005

11/184424

Richard Trauben - Morgan Hill CA, US
Jonathan Sweedler - Los Gatos CA, US
Rajesh Nair - Fremont CA, US

Mistletoe Technologies, Inc. - Cupertino CA

G06F 9/46

718102000

A dispatcher module has a queue to store task requests. The dispatcher also has a task arbiter to select a current task for assignment from the task requests and a unit arbiter to identify and assign the task to an available processing unit, such that the current task is not assigned to a previously-assigned processing unit.

2007002, Jan 25, 2007

Jul 25, 2005

11/189140

Jonathan Sweedler - Los Gatos CA, US

Mistletoe Technologies, Inc. - Cupertino CA

G06F 9/44

712226000

A system and method include identifying a conditional skip instruction, determining when a conditional skip instruction is satisfied according to a result of an associated compare function, and skipping a fixed-number of the instructions defined by the conditional skip instruction when the conditional skip function is satisfied.

2007004, Feb 22, 2007

Jul 19, 2005

11/185223

Jonathan Sweedler - Los Gatos CA, US
Rajesh Nair - Fremont CA, US
Komal Rathi - Sunnyvale CA, US
Kevin Rowett - Cupertino CA, US

Mistletoe Technologies, Inc. - Cupertino CA

G06F 15/16

709227000

A device has an input port to allow the device to receive data. The device also has a parser to parse the data in response to symbols in a parser stack, determine when a symbol is a debug non-terminal symbol, and notify the device via an interrupt. The interrupt causes the device to gather information about the state of the parser at the time of encountering the non-terminal symbol.

5307301, Apr 26, 1994

Apr 13, 1993

8/046642

Jonathan B. Sweedler - Sunnyvale CA

Intel Corporation - Santa Clara CA

G06F 738

364748

A safe instruction recognition method and apparatus for use in a pipelined floating-point processor is described. It is based on the examination of the exponents of each operand. A simple symmetric test, applicable to each exponent, is disclosed using the same fixed upper and lower limits. A parallel safe instruction recognition network is described that allows the simultaneous testing of both operand exponent lower and upper limits. All operands declared safe by this method ensure against floating-point processor overflow and underflow exceptions for add, subtract, multiply and divide operations.