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Joseph J Gajda, 9153 Halley Ct, Poughkeepsie, NY 12601

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53 Halley Ct, Poughkeepsie, NY 12601    512-3109052   

Mars Hill, NC   

Carlsbad, CA   

8400 Laughing Water Ln, Round Rock, TX 78681    512-2184941   

Fishkill, NY   

Manassas, VA   

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Joseph J Gajda

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Position: Design methodology engineer co-op

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Design Methodology Engineer Co-Op

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Design Methodology Engineer Co-Op

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Us Patents

Chip Contacts Without Oxide Discontinuities

US Patent:
4839715, Jun 13, 1989
Filed:
Aug 20, 1987
Appl. No.:
7/087478
Inventors:
Joseph J. Gajda - Wappingers Falls NY
Kris V. Srikrishnan - Wappingers Falls NY
Paul A. Totta - Poughkeepsie NY
Francis G. Trudeau - Wappingers Falls NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 2348
US Classification:
357 71
Abstract:
An integrated circuit chip including a first and a higher second surface levels with an abrupt sidewall step transition therebetween, and having a first layer of a first conductive material disposed over the first surface level and over the second surface level, but terminating on the first surface level in a first end portion which extends up to but does not touch the sidewall. This end portion comprises a conductive material which has been converted to an insulator. A second layer of a second conductive material is disposed on top of the first conductive layer with essentially no conductive material conversion to insulator therein adjacent to the abrupt sidewall transition. In a preferred embodiment, the conductive material is an alloy of aluminum and the end portion is aluminum oxide.

Aluminum-Copper Alloy Evaporated Films With Low Via Resistance

US Patent:
4393096, Jul 12, 1983
Filed:
Sep 20, 1982
Appl. No.:
6/420174
Inventors:
Joseph J. Gajda - Wappingers Falls NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 21285
US Classification:
427 90
Abstract:
Controlling Al. sub. 2 Cu precipitation in copper doped aluminum by evaporating the aluminum metallurgy containing 3 to 4% copper at about 210. degree. C. on SiO. sub. 2 coated semiconductor devices. In multilevel metallurgy sintering can be optionally performed at 400. degree. C. for 75 minutes to cause intermetal diffusion at vias between the metallurgy levels.

Etchant For Silicon Dioxide Films Disposed Atop Silicon Or Metallic Silicides

US Patent:
4230523, Oct 28, 1980
Filed:
Dec 29, 1978
Appl. No.:
5/974573
Inventors:
Joseph J. Gajda - Wappingers Falls NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 21306
US Classification:
156657
Abstract:
An etchant comprising a solution of hydrogen fluoride dissolved in an organic solvent such as glycerine. The solution is substantially free of unbound water and ammonium fluoride. The etchant is particularly suitable for removing silicon dioxide disposed atop a metallic silicide formed in a silicon semiconductor where the silicon may be exposed.

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