Joseph F Rantala, 64Shrewsbury, MA

5388222, Feb 7, 1995

Mar 28, 1994

8/219807

Lawrence A. P. Chisvin - Sudbury MA
John K. Grooms - Webster MA
Joseph F. Rantala - Worcester MA
David W. Hartwell - Boxboro MA

Digital Equipment Corporation - Maynard MA

G06F 1300

395275

Methodology and circuitry for managing read and write commands from nodes to a shared memory resource on a common data bus, including nodes with write-back caches, nodes with write-through caches and nodes without caches.

5680570, Oct 21, 1997

Sep 30, 1994

8/316057

Joseph F. Rantala - Worcester MA
John K. Grooms - Webster MA
Charles F. Cassidy - Northboro MA

Quantum Corporation - Milpitas CA

G06F 1116
G06F 1208

395440

A memory system having volatile storage of data destined for secondary storage and smaller intermediate non-volatile storage of some of the data. The volatile memory is an array of DRAM storage devices integrated with the non-volatile memory array of SRAM devices by a mapping logic unit. The DRAM array stores all the data blocks destined for secondary storage. In contrast, the smaller SRAM array stores only the data requiring safe storage, which typically is a subset of the data stored in the DRAM array. The mapping logic unit manages the use of the SRAM array.