Joseph P Scanlon, 4836 Castle St, San Francisco, CA 94133

5526504, Jun 11, 1996

Dec 15, 1993

8/168822

Peter Y. Hsu - Fremont CA
Joseph T. Scanlon - Sunnyvale CA
Steve J. Ciavaglia - Williston VT

Silicon Graphics, Inc. - Mountain View CA

G06F 1210

395417

A set associative translation lookaside buffer (TLB) that supports variable sized pages without requiring the use of a separate block TLB. The TLB includes a hashing circuit that creates an index into the TLB for a virtual address using different bits from the virtual address depending on the page size of the address, and a comparator that compares virtual address identifiers or portions of virtual address identifiers stored in the TLB to the current virtual address to determine if a translation to the current virtual address is stored in the TLB.

2019026, Aug 29, 2019

Feb 28, 2018

15/907660

- Santa Clara CA, US
- Markham, CA
Ming L. So - Danville CA, US
Philip Ng - Toronto, CA
Xiao Gang Zheng - Sunnyvale CA, US
Felix Ho - Toronto, CA
Joseph Scanlon - Sunnyvale CA, US
Christopher T. Weaver - Boxborough MA, US
Xiaojie He - Austin TX, US
Carl Kittredge Wakeland - Scotts Valley CA, US

G06F 1/32

Systems, apparatuses, and methods for aligning active and idle phases of components in a computing system are disclosed. A computing system includes components that can be forced into an active or idle phase and components that cannot be forced into an active or idle phase. The system implements schemes for aligning the active and idle phases of the components within the system. For example, a timer starts counting when a processor and memory subsystem go from a low power state to an operational state. If the amount of time spent by the processor and memory subsystems in the operational state without transitioning to the low power state exceeds a threshold, the system forces active-to-idle and idle-to-active phase transitions of components in the system in order to cause a realignment of active and idle phases of the various components within the system.