Joydeep M Mitra, 573798 Yosemite Dr, Okemos, MI 48864

6591402, Jul 8, 2003

Mar 17, 2000

09/528088

Rajit Chandra - Cupertino CA
Joydeep Mitra - San Jose CA
Steven B. Parks - Santa Clara CA
Chandrasekhara Somanathan - Milpitas CA

Moscape, Inc. - Santa Clara CA

G06F 1750

716 5

Techniques for analyzing circuit designs based on assertions. An assertion is associated with a circuit structure from the circuit design. The assertion specifies a context of the circuit design in which the circuit structure is to be analyzed, an attribute associated with the circuit structure, and a constraint associated with the attribute. The present invention analyzes the circuit design based on assertions and checks to identify one or more instances of the circuit structure in the circuit design which do not satisfy the constraint specified in the assertion. An assertion may also indicate an action to be performed if the circuit structure does not satisfy the constraint specified in the assertion.

7180210, Feb 20, 2007

Oct 10, 2003

10/685304

Joel Jorgenson - Fargo ND, US
Joydeep Mitra - Las Cruces NM, US
Donald Stuehm - Rochert MN, US
Terry Shaner - Winchester VA, US

H02J 3/46
H02J 9/00

307153, 307 65

A standby generator integration system for efficiently integrating one or more standby generators into an operational power grid. The standby generator integration system includes a control center in communication with a plurality of control units. Each of the control units are in communication with a standby generator, the power grid and a contactor unit. The control unit calculates the hard minimum of the grid voltage and the generator voltage where switching is desired by summing the rectified voltages together. The control unit then initiates the closing of the contactor unit to bring the standby generator online with the power grid.

6449753, Sep 10, 2002

Mar 20, 2000

09/528667

Joydeep Mitra - San Jose CA

Sun Microsystems, Inc. - Santa Clara CA

G06F 945

716 5, 716 6

An automated method of analyzing crosstalk in a digital logic integrated circuit on a digital computer is described. The method uses available software to make an extracted, parameterized netlist from a layout of the integrated circuit. The netlist has gate and black box invocations as well as transistor invocations. Library models are used to find driving resistances and capacitances associated with the gate and black-box invocations. For at least one potential victim wire of the plurality of wires, a subset of the wires of the chip are found to be potential aggressor wires to the victim wire. The aggressor wires are combined into a common aggressor. A risetime of the common aggressor is calculated and used to calculate the magnitude of coupled noise on the victim wire induced by the aggressor wires. An alarm threshold for each potential victim wire is determined based upon the type of logic gate that receives the victim wire. The alarm thresholds for each potential victim wire are compared to the calculated height of a coupled noise on the victim wire to determine which, if any, wires of the design suffer enough crosstalk noise that they should be redesigned.

2015005, Feb 19, 2015

Aug 13, 2014

14/458597

- East Lansing MI, US
Joydeep MITRA - Okemos MI, US

Board of Trustees of Michigan State University - East Lansing MI

G06Q 50/06

700286

An electric power system or power grid is optimized using a computer-implemented tool the represents in computer memory the optimization function and at least one constraint, which the processor operates upon using a linear programming solver algorithm. The constraints are represented in memory as data structures that include both real and reactive power terms, corresponding to at least one of a power flow model and a transmission line model. The transmission line model is represented using a piecewise linear representation. The power flow model may also include for each node in the power system a real power loss term representing transmission line loss allocated to that node.