Judson S Leonard, 79220 Dorset Rd, Newton, MA 02468

7533197, May 12, 2009

Nov 8, 2006

11/594446

Judson S. Leonard - Newton MA, US
David Gingold - Somerville MA, US
Lawrence C. Stewart - Wayland MA, US

SiCortex, Inc. - Maynard MA

G06F 13/28
G06F 15/167

710 22, 710 23, 710 24, 709212

A multi-node computer system with a plurality of interconnected processing nodes, including a method of using DMA engines without page locking by the operating system. The method includes a sending node with a first virtual address space and a receiving node with a second virtual address space. Performing a DMA data transfer operation between the first virtual address space on the sending node and the second virtual address space on the receiving node via a DMA engine, and if the DMA operation refers to a virtual address within the second virtual address space that is not in physical memory, causing the DMA operation to fail. The method includes causing the receiving node to map the referenced virtual address within the second virtual address space to a physical address, and causing the sending node to retry the DMA operation, wherein the retried DMA operation is performed without page locking.

7620954, Nov 17, 2009

Aug 8, 2001

09/924934

Matthew C. Mattina - Hudson MA, US
Carl Ramey - Auburn MA, US
Bongjin Jung - Westford MA, US
Judson Leonard - Newton MA, US

Hewlett-Packard Development Company, L.P. - Houston TX

G06F 3/00
G06F 13/00

719311, 711130, 711131, 711152

Each processor in a distributed shared memory system has an associated memory and a coherence directory. The processor that controls a memory is the Home processor. Under certain conditions, another processor may obtain exclusive control of a data block by issuing a Load Lock instruction, and obtaining a writeable copy of the data block that is stored in the cache of the Owner processor. If the Owner processor does not complete operations on the writeable copy of the data prior to the time that the data block is displaced from the cache, it issues a Victim To Shared message, thereby indicating to the Home processor that it should remain a sharer of the data block. In the event that another processor seeks exclusive rights to the same data block, the Home processor issues an Invalidate message to the Owner processor. When the Owner processor is ready to resume operation on the data block, the Owner processor again obtains exclusive control of the data block by issuing a Read-with Modify Intent Store Conditional instruction to the Home processor. If the Owner processor is still a sharer, a writeable copy of the data block is sent to the Owner processor, who completes modification of the data block and returns it to the Home processor with a Store Conditional instruction.

7660270, Feb 9, 2010

Nov 8, 2006

11/594416

Judson S. Leonard - Newton MA, US
Matthew H. Reilly - Stow MA, US
Lawrence C. Stewart - Wayland MA, US
Washington Taylor - Cambridge MA, US

SiCortex, Inc. - Maynard MA

H04L 12/28

370255, 370254, 370203

Computer systems and methods using efficient module and backplane tiling to interconnect computer nodes via a Kautz-like digraph. A multinode computing system includes a large plurality of computing nodes interconnected via a Kautz topology having order O, diameter n, and degree k. The order equals (k+1)k. The interconnections from a node x to a node y in the topology satisfy the relationship y=(−x*k−j) mod O, where 1≦j≦k, and the computing nodes are arranged onto a plurality of modules. Each module has an equal plurality of computing nodes on it. A majority of the inter-node connections are contained on the plurality of modules and a minority of the inter-node connections are inter-module connections. Inter-module connections are routed among modules in parallel on an inter-module connection plane.

7751344, Jul 6, 2010

Nov 8, 2006

11/594423

Judson S. Leonard - Newton MA, US
Matthew H. Reilly - Stow MA, US
Lawrence C. Stewart - Wayland MA, US
Washington Taylor - Cambridge MA, US

SiCortex, Inc. - Maynard MA

H04L 12/28

370255, 370230, 370231, 370235, 370236, 370237, 370254, 709220, 709221, 709222, 709225, 709226, 709227, 709228, 709229

Computer system and method using a Kautz-like digraph to interconnect computer nodes and having control back channel between nodes. A multinode computing system includes a large plurality of computing nodes interconnected via a Kautz topology having order O, diameter n, and degree k. The order equals (k+1)k; The data interconnections from a node x to a node y in the topology satisfy the relationship y=(−x*k−j) mod O, where 1≦j≦k; and each x,y pair includes a unidirectional control link from node y to node x to convey flow control and error information from a receiving node y to a transmitting node x.

7773616, Aug 10, 2010

Nov 8, 2006

11/594405

Matthew H. Reilly - Stow MA, US
Nitin Godiwala - Boylston MA, US
Judson S. Leonard - Newton MA, US

SiCortex, Inc. - Maynard MA

H04L 12/28
H04L 12/56

370409, 370400, 370401, 370414, 370396, 370397

Systems and methods for communicating on a richly-connected multiprocessor computer system using a pool of buffers for dynamic association with a virtual channel. Packets are communicated in a multiprocessor computer system having a large plurality of processing nodes interconnected by a defined interconnection topology, in which a communication from a source processing node to a target processing node may pass through one or more intermediate nodes en route to the target processing node. A set of virtual channels is associated for each link in the interconnection topology. A first subset of buffers is dedicated for fixed correspondence to virtual channel identifiers, and a second subset of buffers is dedicated for dynamic allocation and assignment to virtual channels.

7773617, Aug 10, 2010

Nov 8, 2006

11/594420

Nitin Godiwala - Boylston MA, US
Judson S. Leonard - Newton MA, US
Matthew H. Reilly - Stow MA, US

SiCortex, Inc. - Maynard MA

H04L 12/28
H04L 12/56

370409, 370397, 370414, 370400

Systems and methods for arbitrating for virtual channels to prevent livelock in richly-connected multiprocessor computer system. Livelock is prevented in a multiprocessor computer system, in which each of a large plurality processing node has input links and egress links. A virtual channel is assigned to convey the communication. Communication data from the plurality of input links is buffered in cross point buffers. A subset of the cross point buffers bids for, and arbitrates, use of the same one egress link. The virtual channel of the selected communication is identified. It is determined whether any of the other communications bidding for use of the egress link are associated with the identified virtual channel and if so whether any communication has been waiting longer than the selected communication. If so, allowing that communication to use the egress link before the selected communication does.

7773618, Aug 10, 2010

Nov 8, 2006

11/594426

Judson S. Leonard - Newton MA, US
Matthew H. Reilly - Stow MA, US
Nitin Godiwala - Boylston MA, US

SiCortex, Inc. - Maynard MA

H04L 12/28
H04L 12/56

370409, 370396, 370400

Systems and methods for preventing deadlock in richly-connected multiprocessor computer system using dynamic assignment of virtual channels. Deadlock is prevented in a multiprocessor computer system having a large plurality of processing nodes interconnected by a defined interconnection topology. Each link in the interconnection topology is associated with a set of virtual channels. Each virtual channel has corresponding communication buffers to store communication data and each virtual channel has an associated virtual channel identifier. Each communication between a source processing node and a target processing node is assigned an initial virtual channel to convey the communication from the source processing node. At an intermediate processing node, a different virtual channel is assigned to convey the communication toward the target processing node, in accordance with pre-defined rules to avoid a cycle of dependency of communication buffer resources.

2007016, Jul 19, 2007

Jan 19, 2006

11/335421

Judson Leonard - Newton MA, US
Matthew Reilly - Stow MA, US

G06F 13/28

711141000

Systems and methods for cache coherency in multi-processor systems. A cache coherency system is used in a multi-processor computer system having a physical memory system in communication with the processors via a communication medium. A processor-side cache memory subsystem is associated with each processor of the multi-processor computer system. The cache coherency system includes a cache tag memory structure having a number of entries substantially equal to the defined number of entries for each processor-side cache memory. Each entry of the cache tag memory structure has at least one field corresponding to each processor-side cache memory subsystem.