Kai C Chan960 84Th Ave, Oakland, CA 94621

6677793, Jan 13, 2004

Feb 3, 2003

10/357827

Kai Keung Chan - Fremont CA
Jung-Sheng Hoei - Newark CA
Pankaj Joshi - Milpitas CA
Leo Fang - Belmont CA

LSI Logic Corporation - Milpitas CA

H03L 706

327158, 327291

An automatic delay matching circuit for a data serializer includes a phase-locked loop for synthesizing a transmitter clock signal for an external circuit, a phase interpolator coupled to the phase-locked loop for delaying or advancing the transmitter clock signal in response to a phase control signal to generate a delayed or advanced transmitter clock signal for the data serializer, a phase detector for measuring a phase difference between the delayed or advanced transmitter clock signal further delayed through the data serializer and the transmitter clock signal delayed through an external circuit, and a loop filter coupled to the phase detector for generating the phase control signal as a function of the phase difference between the delayed or advanced transmitter clock signal further delayed through the data serializer and the transmitter clock signal delayed through the external circuit.

7974033, Jul 5, 2011

Apr 13, 2007

11/787230

Kwok W. Yeung - Milpitas CA, US
Kai Keung Chan - Fremont CA, US
Paul K. Lai - San Jose CA, US

Link—A—Media Devices Corporation - Santa Clara CA

G11B 5/09
G11B 5/02

360 50, 360 48, 360 55

Injecting pad bits during a read operation to improve format efficiency is disclosed. In some embodiments, a pad sequence associated with error correction is not stored in a sector on a disk. Instead, the pad sequence is merged at a read channel with data stored in a sector that is accessed by the read channel.

8489971, Jul 16, 2013

May 27, 2011

13/117955

Kai Keung Chan - Fremont CA, US
Kin Man Ng - Cupertino CA, US
Jason Bellorado - Santa Clara CA, US

SK hynix memory solutions inc. - San Jose CA

H03M 13/03

714795

A system for adapting coefficients of a soft output Viterbi algorithm (SOVA) is disclosed. The system includes a receiver configured to select an output of an SOVA detector at least in part based on a criterion. The receiver is configured to store the selected output of the SOVA detector. The receiver is further configured to store a signal that corresponds to the stored selected output of the SOVA detector, wherein the input to the SOVA detector is derived from the signal. The receiver is further configured to adapt a plurality of coefficients of the SOVA detector at least in part based on the stored selected output of the SOVA detector, the stored signal, and a corresponding data pattern. The system includes an interface coupled to the receiver and configured to receive samples.

8570680, Oct 29, 2013

May 23, 2011

13/113926

Kwok W. Yeung - Milpitas CA, US
Kai Keung Chan - Fremont CA, US
Paul K. Lai - San Jose CA, US

SK hynix memory solutions inc. - San Jose CA

G11B 5/09
G11B 5/02

360 50, 360 48, 360 55

Injecting pad bits during a read operation to improve format efficiency is disclosed. In some embodiments, a pad sequence associated with error correction is not stored in a sector on a disk. Instead, the pad sequence is merged at a read channel with data stored in a sector that is accessed by the read channel.

8631311, Jan 14, 2014

Apr 23, 2012

13/453729

Kai Keung Chan - Fremont CA, US
Yu Kou - San Jose CA, US
Wing Hui - San Jose CA, US

SK hynix memory solutions inc. - San Jose CA

G06F 11/00

714799, 714769

A method for recovering data is disclosed. A sensed analog signal is converted into digital samples using an analog-to-digital converter (ADC). The digital samples are processed into processed digital samples using a first filter. The processed digital samples are decoded into decoded data. Whether the decoded data is acceptable is then determined. The processed digital samples are fed back to the first filter using a reprocessing circuit such that the processed digital samples are reprocessed into reprocessed digital samples in the event that the decoded data is unacceptable. A set of reprocessing coefficients is provided for the first filter to reprocess the processed digital samples.

4527907, Jul 9, 1985

Sep 6, 1983

6/529301

Kai Y. Chan - Milpitas CA

Fairchild Camera and Instrument Corporation - San Jose CA

G04F 800

368118

Method and apparatus are provided for measuring the settling time, relative to a reference time, of an analog signal having a varying amplitude. The apparatus includes a pair of comparators U1 and U2 for comparing the amplitude of the analog signal with first and second reference signals V. sub. Ref 1 and V. sub. Ref 2. The comparators U1 and U2 are connected to edge detector 22 which supplies a reset signal to a second counter 26 whenever the amplitude of the analog signal is not between the first and second reference signals. Oscillator 32 drives counters 25 and 26 which count pulses from oscillator beginning at the reference time and continuing until the second counter 26 contains a predetermined count. Because the second counter 26 is reset by the edge detector 22 whenever the analog waveform exceeds either of the reference signals, the difference between counter 25 and counter 26 at any subsequent time after the waveform has settled will be the settling time of the analog waveform.

4718018, Jan 5, 1988

Nov 21, 1985

6/800472

Edwin A. Sloane - Los Altos CA
Kai Y. Chan - Milpitas CA
David D. Yau - San Jose CA

Fairchild Semiconductor Corporation - Cupertino CA

G06F 1520
H04N 1700

364480

A digital test system for generating a test signal in the form of an amplitude and/or phase modulated sinusoidal signal at a given carrier frequency is disclosed. Arbitrary amplitude and phase modulation functions may be selected and are provided to the system in the form of digitally encoded data streams. The system does not require a digital multiplier. A signal in the form of an unmodulated carrier signal may also be generated.

2018006, Mar 1, 2018

Feb 2, 2015

14/612076

Kai Keung Chan - Fremont CA, US
David Tsang - Los Altos CA, US
Chao-Chiang Chen - Cupertino CA, US

Agate Logic Inc. - Santa Clara CA

H03K 19/0175
H03K 19/02
H03K 19/177

A logic processing device, containing an application specific integrated circuit (“ASIC”) and field programmable gate array (“FPGA”), capable of automatically interfacing between ASIC and FPGA is disclosed. The logic processing device, in one aspect, includes a phase adjustment circuit, ASIC, and configurable logic circuit (“CLC”) wherein the CLC can be an FPGA. While ASIC is able to perform a specific function in accordance with an ASIC clock domain, the CLC is capable of performing a programmable logic function in accordance with an FPGA clock domain. The phase adjustment circuit is used to automatically facilitate a communication between the ASIC and the CLC in accordance with the ASIC clock domain and the FPGA clock domain.