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Karl D Schuh, 61131 Molina Dr, Santa Cruz, CA 95060

Karl Schuh Phones & Addresses

131 Molina Dr, Santa Cruz, CA 95060    831-4230556    831-4235957   

405 Esmeralda Ct, Santa Cruz, CA 95060    831-4230556   

Bonny Doon, CA   

San Jose, CA   

San Luis Obispo, CA   

Livingston, TX   

Mentions for Karl D Schuh

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Resumes

Karl Schuh Photo 13

Senior Manager Firmware Architecture

Location:
San Francisco, CA
Industry:
Computer Software
Work:
Micron Inc
Senior Manager Firmware Architecture
Lsi Corporation
Senior Manager
Lsi Corporation Jan 2012 - Apr 2013
Principal Firmware Engineer
Sandforce Jun 2009 - Oct 2012
Principal Engineer, Software
Seagate Technology May 2006 - Jun 2009
Senior Staff Software Engineer - Technology
Maxtor Nov 2004 - May 2006
Senior Staff Firmware Engineer
Altera Jun 2003 - Nov 2004
Senior Mts Engineer
Coalsere 2001 - 2003
Software Architect
Apt Technologies 1998 - 2000
Software Consultant
Nexcom Technology 1997 - 1998
Firmware Consultant
Aura Associates 1992 - 1994
Senior Engineer
Seagate Technology 1987 - 1991
Firmware Engineer
Education:
California Polytechnic State University - San Luis Obispo 1981 - 1987
Bachelors, Bachelor of Science In Computer Science, Computer Science
Skills:
Firmware, Sata, Embedded Systems, Debugging, Ssd, Embedded Software, Device Drivers, Soc, Scsi, Logic Analyzer, Asic, Fpga, Pcie, C, Rtos, Processors, Arm, Microprocessors, Flash Memory, Digital Signal Processors, Fibre Channel, Usb, Hardware
Karl Schuh Photo 14

Karl Schuh

Publications & IP owners

Us Patents

Distributed Cache Between Servers Of A Network

US Patent:
7254617, Aug 7, 2007
Filed:
Dec 6, 2002
Appl. No.:
10/313861
Inventors:
Karl Schuh - Santa Cruz CA, US
Chris Hawkinson - Fullerton CA, US
Scott Ruple - Gilbert AZ, US
Tom Volden - Newport Beach CA, US
International Classification:
G06F 9/00
G06F 12/00
US Classification:
709214, 709216, 709205, 709217, 711118, 711120, 711148
Abstract:
A distributed cache module that allows for a distributed cache between multiple servers of a network without using a central cache manager. The distributed cache module transmits each message with a logical timestamp. The distributed cache module of a server that receives the message will delay forwarding of the message to, for example, a client computer, if preceding timestamps are not received. This insures a correct order of timestamped messages without requiring a central manager to allocate and control the transmission of the messages within the network. Each distributed cache module will request and possibly retrieve data from the cache of another server in response to a file request for the data. The data of a file may be accessed by a plurality of servers joined in a file context.

Distributed Cache Between Servers Of A Network

US Patent:
2008018, Aug 7, 2008
Filed:
Jul 28, 2007
Appl. No.:
11/829886
Inventors:
Karl Schuh - Santa Cruz CA, US
Chris Hawkinson - Fullerton CA, US
Scott Ruple - Gilbert AZ, US
Tom Volden - Newport Beach CA, US
International Classification:
G06F 15/167
US Classification:
709214
Abstract:
A distributed cache module that allows for a distributed cache between multiple servers of a network without using a central cache manager. The distributed cache module transmits each message with a logical timestamp. The distributed cache module of a server that receives the message will delay forwarding of the message to, for example, a client computer, if preceding timestamps are not received. This insures a correct order of timestamped messages without requiring a central manager to allocate and control the transmission of the messages within the network. Each distributed cache module will request and possibly retrieve data from the cache of another server in response to a file request for the data. The data of a file may be accessed by a plurality of servers joined in a file context.

Solid-State Disk Manufacturing Self Test

US Patent:
2013012, May 16, 2013
Filed:
Mar 30, 2012
Appl. No.:
13/436639
Inventors:
Karl David SCHUH - Santa Cruz CA, US
Karl Huan-Yao KO - Sunnyvale CA, US
Aloysius C. Ashley WIJEYERATNAM - Newark CA, US
Steven GASKILL - Campbell CA, US
Thad OMURA - Los Altos CA, US
Sumit PURI - Fremont CA, US
Jeremy Isaac Nathaniel WERNER - San Jose CA, US
Assignee:
LSI CORPORATION - Milpitas CA
International Classification:
G11C 29/08
US Classification:
714718
Abstract:
A Solid-State Disk (SSD) Manufacturing Self Test (MST) capability enables an SSD manufacturer to generate and load tests onto SSDs, run the tests, and gather results. The SSDs self execute the loaded tests when powered up. The self executing is while coupled to a host that loaded the tests or while coupled to a rack unable to load the tests but enabled to provide power to the SSDs. The rack is optionally cost-reduced to enable cost-efficient parallel testing of relatively larger numbers of SSDs for production. The host writes the tests to an ‘input’ SMART log of each SSD, and each SSD writes results to a respective included ‘output’ SMART log. The commands include write drive, erase drive, SATA PHY burn-in, delay, and stress mode. The SSD MST capability is optionally used in conjunction with an SSD virtual manufacturing model.

Apparatus And Method For Preventing Data Corruption In Disk Drives From Mechanical Shock During Write Operations

US Patent:
5333138, Jul 26, 1994
Filed:
Mar 11, 1992
Appl. No.:
7/849740
Inventors:
John H. Richards - San Jose CA
Karl D. Schuh - San Jose CA
Assignee:
MiniStor Peripherals International Limited - San Jose CA
International Classification:
G06F 1100
G11B 1504
US Classification:
371 7
Abstract:
Apparatus for preventing data corruption on a disk due to mechanical shock occurring during the write process to the disk includes a mechanical shock sensor to sense mechanical shocks having a magnitude exceeding a predetermined threshold. Write disable circuitry responsive to the mechanical shock sensor interrupts the write current to the disk drive write head. Repositioning circuitry then repositions the data head over the original data track and the incomplete data that was interrupted by the mechanical shock is rewritten. A method for preventing data corruption on a disk due to mechanical shock experienced by a disk drive during the write process to the disk includes the steps of sensing a mechanical shock having a magnitude exceeding a predetermined threshold; storing information identifying the data being written at the onset of the sensed shock; interrupting the write current to the write head; repositioning the data head to the original track; and rewriting the data which was interrupted because of the sensed shock.

Disc Drive Translation And Defect Management Apparatus And Method

US Patent:
5367652, Nov 22, 1994
Filed:
Feb 2, 1990
Appl. No.:
7/474474
Inventors:
Jeffrey A. Golden - Boulder Creek CA
Karl D. Schuh - Scotts Valley CA
International Classification:
G11B 1518
G06F 306
US Classification:
395499
Abstract:
A disc drive translation and defect management method and apparatus. The method and apparatus includes an index table to translate a host computer's logical cylinder request into an arbitrarily designated physical cylinder location in the disc drive system. Once the physical cylinder is located, the physical head and sector location is determined with a quick, relatively simple mathematical translation. If a defect is present on the indexed physical cylinder in question, the index table provides a defect flag and a pointer which points into a predetermined entry of a defect table. The selected entry in the defect table provides a defect offset value for the physical location in question. The offset value is added to the physical cylinder, head and sector location to push it into a defect-free physical location.

Voltage Bin Calibration Based On A Temporary Votlage Shift Offset

US Patent:
2022039, Dec 8, 2022
Filed:
Aug 18, 2022
Appl. No.:
17/820792
Inventors:
- Boise ID, US
Karl Schuh - Santa Cruz CA, US
Mustafa N. Kaynak - San Diego CA, US
Xiangang Luo - Fremont CA, US
Shane Nowell - Boise ID, US
Devin Batutis - San Jose CA, US
Sivagnanam Parthasarathy - Carlsbad CA, US
Sampath Ratnam - Boise ID, US
Jiangang Wu - Milpitas CA, US
Peter Feeley - Boise ID, US
International Classification:
G11C 16/30
G11C 7/04
G11C 16/26
G11C 16/34
G11C 16/32
G11C 16/10
Abstract:
A voltage shift for memory cells of a block family at a memory device is measured. The block family is associated with a first voltage offset. An adjusted amount of voltage shift is determined for the memory cells based on the measured voltage shift and a temporary voltage shift offset associated with a difference between a current temperature and a prior temperature for the memory device. The block family is associated with a second voltage offset in view of the adjusted voltage shift.

Voltage Bin Selection For Blocks Of A Memory Device After Power Up Of The Memory Device

US Patent:
2022038, Dec 1, 2022
Filed:
Aug 8, 2022
Appl. No.:
17/883538
Inventors:
- Boise ID, US
Sampath K. RATNAM - Boise ID, US
Shane NOWELL - Boise ID, US
Sivagnanam PARTHASARATHY - Carlsbad CA, US
Mustafa N. KAYNAK - San Diego CA, US
Karl D. SCHUH - Santa Cruz CA, US
Peter FEELEY - Boise ID, US
Jiangang WU - Milpitas CA, US
International Classification:
G11C 16/10
G11C 16/20
G11C 16/32
G11C 16/30
G11C 16/26
G11C 16/34
Abstract:
A processing device of a memory sub-system is configured to detect a power on event that is associated with a memory device and indicates that power has been restored to the memory device; estimate a duration of a power off state preceding the power on event associated with the memory device; and update voltage bin assignments of a plurality of blocks associated with the memory device based on the duration of the power off state.

Multi-Tier Threshold Voltage Offset Bin Calibration

US Patent:
2022037, Nov 24, 2022
Filed:
Aug 4, 2022
Appl. No.:
17/880980
Inventors:
- Boise ID, US
Shane Nowell - Boise ID, US
Mustafa N. Kaynak - San Diego CA, US
Karl D. Schuh - Santa Cruz CA, US
Jiangang Wu - Milpitas CA, US
Devin M. Batutis - San Jose CA, US
Xiangang Luo - Fremont CA, US
International Classification:
G11C 16/34
G06F 3/06
G06F 11/07
G11C 16/26
Abstract:
A system includes a memory device and a processing device. The processing device performs, at a first frequency, a first scan of a page of a block family that measures a first data state metric and identifies a specific bin corresponding to a measured value for the first data state metric. Processing device updates a bin, to which the page is assigned, to match the specific bin. Processing device performs, at a second frequency higher than the first frequency, a second scan of the page to measure a second data state metric for read operations performed using a threshold voltage offset value from each of multiple bins. Processing device updates the bin, to which the page is assigned for the specified die, to match a second bin having the threshold voltage offset value that yields a lowest read bit error rate from the second scan.

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