Karl A Selander, 55New Hamburg, NY

6356114, Mar 12, 2002

Jan 16, 2001

09/761049

Karl Selander - Hopewell Junction NY

International Business Machines Corporation - Armonk NY

H03K 19094

326 83, 326 66, 326 86, 326 63

An apparatus for receiving an input clock signal to an integrated circuit device is disclosed. In an exemplary embodiment of the invention, the apparatus includes a CMOS receiver configured to receive the input clock signal and a PECL receiver configured to receive the input clock signal. The PECL receiver shares a common output node with the CMOS receiver. A receiver selection mechanism is coupled to the CMOS receiver and the PECL receiver, with the receiver selection mechanism alternatively activating or deactivating the CMOS receiver and the PECL receiver.

6680681, Jan 20, 2004

May 8, 2003

10/249795

Louis L. Hsu - Fishkill NY
William R. Kelly - Verbank NY
Joseph Natonio - Poughkeepsie NY
Karl D. Selander - Hopewell Junction NY
Michael A. Sorna - Hopewell Junction NY

International Business Machines Corporation - Armonk NY

H03M 110

341144, 341120

A transmitter for driving a transmission medium employs pre-distortion to predistort the signals leaving the driver so that they will have an acceptable shape when they reach their destination and have been distorted by imperfections in the transmission medium. The change to pulse height is accomplished by means of a current steering unit that directs a controllable amount of current into the line for each pulse while maintaining the total sum of current that is generated constant in order to reduce noise. Control coefficients for the current steering unit are manipulated in an nxm register that automatically maintains the total number of bits constant while bits are moved from a location that controls a first current driver to a location that controls a second current driver with different properties.

6891357, May 10, 2005

Apr 17, 2003

10/249545

Hibourahima Camara - Wappingers Falls NY, US
Louis Lu-Chen Hsu - Fishkill NY, US
Karl D. Selander - Hopewell Junction NY, US
Michael A. Sorna - Hopewell Junction NY, US

International Business Machines Corporation - Armonk NY

G05F003/16
G05F001/10

323316, 327535

As disclosed herein, systems and methods are provided for generating and distributing a plurality of reference currents on an integrated circuit. In a particular embodiment, an integrated circuit is disclosed which includes a reference current generator adapted to generate a plurality of reference currents. Such circuit includes an operational amplifier coupled to receive, at a first polarity input, a reference voltage, and a first transistor Qhaving a biasing input coupled to an output of the operational amplifier. The first transistor also has an output coupled to a fixed potential through a first resistor R, and the output of the first transistor Qis further coupled as feedback to a second polarity input of the operational amplifier. One or more second transistors Qi are provided in the circuit, each of which has a biasing input coupled to the output of the operational amplifier, and an output coupled to the fixed potential through a respective second resistor Ri. In order to conserve chip area and power, the outputs of the second transistors Qi are not coupled as feedback to the operational amplifier.

6937054, Aug 30, 2005

May 30, 2003

10/250043

Louis L. Hsu - Fishkill NY, US
Karl D. Selander - Hopewell Junction NY, US
Michael A. Sorna - Hopewell Junction NY, US
William F. Washburn - Hyde Park NY, US
Huihao H. Xu - Brooklyn NY, US
Steven J. Zier - Hopewell Junction NY, US

International Business Machines Corporation - Armonk NY

H03K019/003

326 30, 326 86, 326126, 326115, 326127, 327108

Methods and structures are disclosed herein for programmably adjusting a peaking function of a differential signal receiver. The disclosed method includes inputting a pair of differential signals to a pair of input transistors coupled to conduct currents differentially between a pair of load impedances and a pair of tail transistors. The impedance of an adjustable shunt impedance element between the tail transistors of the receiver is varied by programming signal input, such that higher current is conducted over a peaking range of frequencies. In a disclosed structural embodiment, an integrated circuit is provided having a programmable peaking receiver. The programmable peaking receiver includes a pair of input transistors coupled to conduct differentially according to a pair of differential inputs applied to the pair of input transistors. Each of the input transistors produces an output in accordance with the differential input applied thereto. The programmable peaking receiver also includes a pair of tail transistors, coupled to draw current from the input transistors, and a programmably adjustable impedance element coupled between current-conducting nodes of the tail transistors.

6980824, Dec 27, 2005

Apr 17, 2003

10/249546

Louis L. Hsu - Fishkill NY, US
Brian L. Ji - Fishkill NY, US
Karl D. Selander - Hopewell Junction NY, US
Michael A. Sorna - Hopewell Junction NY, US

International Business Machines Corporation - Armonk NY

H04B007/00

455522, 455 69, 375358

A method and system are disclosed herein for determining optimum power level settings for a transmitter and receiver pair of a communication system having a plurality of transmitter and receiver pairs, as determined with respect to bit error rate. In the method disclosed herein, the power levels of a transmitter and a receiver pair coupled to communicate over a duplex communication link are set to initial values. The bit error rate is then determined over the link. Then, the power level of the transmitter, the receiver, or both, is altered, incrementally, and the effect upon the bit error rate is determined. When an improvement appears in the bit error rate at an altered power level, the power level of the transmitter, the receiver or both, are set to the altered power level at which the improvement is found. The steps of incrementally altering power levels, determining the bit error rate, and establishing new power level settings when there is an improvement are repeated until power levels are determined at which the bit error rate is optimized.

7102392, Sep 5, 2006

Jan 18, 2005

10/905704

Louis L. Hsu - Fishkill NY, US
Karl D. Selander - Hopewell Junction NY, US
Michael A. Sorna - Hopewell Junction NY, US

International Business Machines Corporation - Armonk NY

H03K 5/19

327 20, 327 65

An improved signal detector system implementable in a high-speed SerDes receiver core that is able to detect valid signals from noise signals with a much tighter tolerance. The signal detector system improves upon the prior art designs by implementing modifications including: (1) the use of two peaking amplifiers for both (differential) input signals and reference to track and cancel gain variation; and, (2) the reduction of current mirroring stages to cut down current mapping error.

7132821, Nov 7, 2006

Apr 11, 2005

11/103314

Hibourahima Camara - Wappingers Falls NY, US
Louis Lu-Chen Hsu - Fishkill NY, US
Karl D. Selander - Hopewell Junction NY, US
Michael A. Sorna - Hopewell Junction NY, US

International Business Machines Corporation - Armonk NY

G05F 3/16
G05F 1/10
H03F 3/45

323315, 323316, 327539

Systems are provided for generating and distributing a plurality of reference currents on an integrated circuit. More particularly, an integrated circuit is provided which includes a reference current generating system. The reference current generating system includes a first reference current generator disposed at a first location of the integrated circuit which is operable to generate a plurality of first reference currents. A plurality of second reference current generators are disposed at a plurality of second locations of the integrated circuit. Each of the second reference current generators are operable to generate a second reference current from one of the plurality of first reference currents. In a particular example, the first location at which the first reference current generator is disposed is a central location and the second locations are disposed remote from the first location.

7205830, Apr 17, 2007

Jan 4, 2005

10/905436

Gautam Gangasani - Hopewell Junction NY, US
Louis L. Hsu - Fishkill NY, US
Karl D. Selander - Hopewell Junction NY, US
Steven J. Zier - Hopewell Junction NY, US

International Business Machines Corporation - Armonk NY

G05F 1/10

327543, 327389

Circuits and methods are provided for reducing the voltage stress applied to the drain to source conduction path of an FET and/or to reduce the stress to the gate oxide of an FET which may have a thin gate oxide. Thus, in a current mirror circuit disclosed herein, a first field effect transistor (FET) has a first gate and a first drain, in which the first drain is conductively connected to a current source for conducting a first current. The current mirror circuit also includes at least one second FET having a second gate conductively connected to the first gate, in which the second FET is operable to output a second current in fixed proportion to the first current. A switching element having a first conductive terminal is connected to the first gate and to the second gate, the second conductive terminal being connected to the first drain of the first FET. A switching network is operable to controllably switch the first and second FETs and the third switching element between a powered on state in which the first and second currents are conducted and the third switching element is conducting, and a powered off state in which the first and second currents are not conducted and the third switching element is nonconducting such that the same drain to source voltage stress is applied to both first and second FETs.