Keith S Ford, 66Glendale, AZ

6493283, Dec 10, 2002

Nov 22, 2000

09/721324

Keith A. Ford - Colorado Springs CO
Iulian C. Gradinariu - Colorado Springs CO
Bogdan I. Georgescu - Colorado Springs CO
Sean B. Mulholland - Colorado Springs CO
John J. Silver - Monument CO
Danny L. Rose - Monument CO

Cypress Semiconductor Corp. - San Jose CA

G11C 800

36523003, 365 63, 36523005

A circuit comprising a plurality of groups of memory cells and a control circuit. The plurality of groups of memory cells may each (i) have a first and a second bitline and (ii) configured to read and write data to one or more of the plurality of groups of memory cells. The control circuit may be configured to select an active group of the plurality of groups in response to one or more control signals. The control circuit may be implemented within the groups of memory cells.

6530040, Mar 4, 2003

Sep 22, 1999

09/401614

Iulian C. Gradinariu - Colorado Springs CO
John J. Silver - Monument CO
Keith A. Ford - Colorado Springs CO
Sean B. Mulholland - Colorado Springs CO

Cypress Semiconductor Corp. - San Jose CA

G06F 1126

714 42, 714718

An asynchronous memory device includes parallel test circuitry configured to interface with a single-ended output data path of the memory device and, in some cases, to provide a measure of a slowest cell access time for the memory device. The parallel test circuitry may include first circuitry configured to receive logic signals from a plurality of cells of the memory device and to provide first output signals indicative of logic states of the plurality of cells; and second circuitry configured to receive the first output signals and to produce a second output signal indicative of the logic states of the first output signals therefrom. For example, the first circuitry and the second circuitry may be configured as a wired NAND and wired NOR combination. In some cases, one or more of the cells may be included within a redundant row or column of the memory device. The first circuitry may include one or more circuits, each including an input path from a first number of the plurality of cells and configured to provide at least one of the first output signals.

6535437, Mar 18, 2003

Jun 15, 2001

09/882898

John J. Silver - Monument CO
Iulian C. Gradinariu - Colorado Springs CO
Bogdan I. Georgescu - Colorado Springs CO
Keith A. Ford - Colorado Springs CO
Sean B. Mulholland - Colorado Springs CO
Danny L. Rose - Monument CO

Cypress Semiconductor Corp. - San Jose CA

G11C 700

365200, 365226, 365227

A circuit comprising a memory array and a logic circuit. The memory array may be configured to read or write data in response to (i) one or more enable signals and (ii) one or more control signals. The logic circuit may be configured to generate the enable signals in response to one or more address signals. De-assertion of one or more of the enable signals generally reduces current consumption in the memory array.

6629185, Sep 30, 2003

Dec 6, 1999

09/455272

John Silver - Monument CO
Iulian Gradinariu - Colorado Springs CO
Keith Ford - Colorado Springs CO
Sean Mulholland - Colorado Springs CO

Cypress Semiconductor Corp. - San Jose CA

G06F 1314

710307

An apparatus comprising a first bus, a second bus, a memory and one or more interconnections. The memory may be connected to the first bus and the second bus and may be configured to transfer data over the first bus and the second bus. The one or more interconnections may be connected between one or more data lines of the first bus and the second bus to control a bit-width of the first and second buses.

6662315, Dec 9, 2003

Nov 26, 2002

10/305699

Iulian C. Gradinariu - Colorado Springs CO
John J. Silver - Monument CO
Keith A. Ford - Colorado Springs CO
Sean B. Mulholland - Colorado Springs CO

Cypress Semiconductor Corporation - San Jose CA

G06F 1100

714 42

An asynchronous memory device includes parallel test circuitry configured to interface with a single-ended output data path of the memory device and, in some cases, to provide a measure of a slowest cell access time for the memory device. The parallel test circuitry may include first circuitry configured to receive logic signals from a plurality of cells of the memory device and to provide first output signals indicative of logic states of the plurality of cells; and second circuitry configured to receive the first output signals and to produce a second output signal indicative of the logic states of the first output signals therefrom. For example, the first circuitry and the second circuitry may be configured as a wired NAND and wired NOR combination. In some cases, one or more of the cells may be included within a redundant row or column of the memory device. The first circuitry may include one or more circuits, each including an input path from a first number of the plurality of cells and configured to provide at least one of the first output signals.

6674682, Jan 6, 2004

Jul 19, 2002

10/199560

Keith A. Ford - Colorado Springs CO
Iulian C. Gradinariu - Colorado Springs CO
Bogdan I. Georgescu - Colorado Springs CO
Sean B. Mulholland - Colorado Springs CO
John J. Silver - Monument CO
Danny L. Rose - Monument CO

Cypress Semiconductor Corp. - San Jose CA

G11C 800

36523003, 365226

A method for providing at least 2 Meg of SRAM cells having a maximum average operating current of approximately 9. 43 mA comprising the steps of (A) providing an address path configured to consume a maximum average operating current of approximately 2. 38 mA, (B) providing one or more sense amplifiers configured to consume a maximum average operating current of approximately 0. 91 mA, (C) providing one or more bitlines configured to consume a maximum average operating current of approximately 0. 94 mA and (D) providing a Q path configured to consume a maximum average operating current of approximately 0. 61 mA.

6324107, Nov 27, 2001

Aug 15, 2000

9/639454

James D. Allan - Colorado Springs CO
John J. Silver - Colorado Springs CO
Keith A. Ford - Colorado Springs CO

Cypress Semiconductor Corporation - San Jose CA

G11C 700

365201

An asynchronous memory device includes parallel test circuitry configured to provide a measure of a slowest bit access time for the device. The parallel test circuitry may include first circuitry configured to receive logic signals from a plurality of cells of the device and to provide first output signals indicative of logic states of the plurality of cells. The parallel test circuitry may also include second circuitry configured to receive the first output signals and to produce second output signals indicative of logic states of the first output signals therefrom. The parallel test circuitry may be the same circuitry used in the read path of the memory device, and may be configured such that the second output signals are produced at the slowest bit access time. The plurality of cells tested may include a redundant cell of the device. Such redundancy is transparent to the test circuitry.

5675542, Oct 7, 1997

Jun 28, 1996

8/671671

Keith A. Ford - Colorado Springs CO

Cypress Semiconductor Corp. - San Jose CA

G11C 700
G11C 702

36518911

A method and apparatus for reducing noise in a memory bit-line pull-up circuit. The memory bit-line pull-up circuit includes a first reference line, a second reference line, a first capacitor, a gating device, and a pull-down circuit. The circuit may further include a load transistor coupled between the first reference line and a first voltage conduit, which generally maintains the voltage on the first reference line at Vcc-Vt, and a second capacitor and the load transistor providing a pull-up path for the voltage on the first reference line when Vcc increases and the first capacitor. The pull-down circuit provides a pull-down path for the voltage on the first reference line when Vcc decreases. The first capacitor provides a pull-up path for the voltage on the second reference line. A first gating device couples a bit-line to the first reference line.