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Keith K Wong7222 E Gainey Ranch Rd UNIT 128, Scottsdale, AZ 85258

Keith Wong Phones & Addresses

7222 E Gainey Ranch Rd UNIT 128, Scottsdale, AZ 85258    480-4959391   

6348 Doubletree Ranch Rd, Paradise Valley, AZ 85253    480-3482523   

Maricopa, AZ   

White Plains, NY   

Paradise Vly, AZ   

Phoenix, AZ   

Billerica, MA   

7833 E Vista Dr, Scottsdale, AZ 85250    614-8463999   

Work

Company: Bristol-myers squibb co. (formerly dupont pharmaceuticals) - New York, NY 2008 Position: Senior territory business manager, neuroscience specialty

Education

School / High School: FORDHAM UNIVERSITY- New York, NY 2006 Specialities: MBA in Finance and Management

Mentions for Keith K Wong

Career records & work history

Medicine Doctors

Keith Y. Wong

Specialties:
Optometry
Work:
Center For Sight
1144 Norman Dr STE 102, Manteca, CA 95336
209-8231152 (phone) 209-8233376 (fax)
Site
Center For Sight
1805 N California St STE 101, Stockton, CA 95204
209-9485515 (phone) 209-9489321 (fax)
Site
Procedures:
Ophthalmological Exam
Languages:
English, Spanish
Description:
Dr. Wong works in Manteca, CA and 1 other location and specializes in Optometry. Dr. Wong is affiliated with Dignity Health Saint Josephs Medical Center and Doctors Hospital Of Manteca.

License Records

Keith Wong

Licenses:
License #: 33625 - Active
Category: Professional
Issued Date: Apr 13, 1999
Expiration Date: Jun 30, 2017

Keith Wong resumes & CV records

Resumes

Keith Wong Photo 48

Chief Executive Officer At Talguu Inc

Location:
7222 east Gainey Ranch Rd, Scottsdale, AZ 85258
Industry:
Internet
Work:
EastBridge Investment Group Corp
CEO
Education:
Harvard Business School 2014 - 2014
Harvard Business School 2008 - 2011
Harvard Business School Executive Education
Northeastern University
Masters, Master of Arts, Electrical Engineering
Rutgers University
Bachelors, Electrical Engineering
Skills:
Management, Strategic Planning, Leadership, Business Strategy, Project Management, Business Development
Languages:
English
Mandarin
Cantonese
Keith Wong Photo 49

Keith Wong

Keith Wong Photo 50

Keith Mexicali Wong

Keith Wong Photo 51

Keith Wong

Keith Wong Photo 52

Keith Wong

Keith Wong Photo 53

Keith Wong

Keith Wong Photo 54

Keith Wong

Keith Wong Photo 55

Keith Wong

Publications & IP owners

Us Patents

Method For Forming A Tin Layer On Top Of A Metal Silicide Layer In A Semiconductor Structure And Structure Formed

US Patent:
6436823, Aug 20, 2002
Filed:
Oct 5, 2000
Appl. No.:
09/679738
Inventors:
Cyril Cabral, Jr. - Ossining NY
Chung-Ping Eng - Hopewell Junction NY
Lynne Marie Gignac - Beacon NY
Christian Lavoie - Ossining NY
Patricia ONeil - Wappingers Falls NY
Kirk David Peterson - Essex Junction VT
Tina Wagner - Newburgh NY
Yun-Yu Wang - Poughquag NY
Keith Wong - Wappingers Falls NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 2144
US Classification:
438686, 438570, 438637, 438653, 438680, 257384
Abstract:
A method for forming a TiN layer on top of a metal silicide layer in a semiconductor structure without the formation of a thick amorphous layer containing Ti, Co and Si and the structure formed are provided. In the method, after a Ti layer is deposited on top of a metal silidide layer, a dual-step annealing process is conducted in which a low temperature annealing in a forming gas (or ammonia) at a temperature not higher than 500Â C. is first conducted for less than 2 hours followed by a high temperature annealing in a nitrogen-containing gas (or ammonia) at a second temperature not lower than 500Â for less than 2 hours to form the TiN layer. The present invention method prevents the problem usually caused by a thick amorphous material layer of TiâSiâCo which produces weakly bonded Ti which reacts with fluorine atoms from WF during a subsequent CVD W deposition process and causes liner failure due to a volume expansion of the amorphous material. The maximum thickness of the amorphous material layer formed by the present invention method is less than 5 nm which minimizes the line failure problem.

Communication System For Communicating Common Data To A Plurality Of Reception Devices

US Patent:
6816061, Nov 9, 2004
Filed:
Sep 15, 2000
Appl. No.:
09/663533
Inventors:
Keith K. Wong - Paradise Valley AZ, 85253
International Classification:
G08B 522
US Classification:
340 746, 340 759, 340 758, 340 748, 340 755, 34082529, 340 751, 340 752
Abstract:
A communication system ( ) uses commercial, mass market paging transmission facilities ( ) to deliver messages ( â) to a population of reception devices ( ). Each reception device ( ) includes a display screen ( ) at which lines ( ) of national and local news and advertising, a banner advertising box ( ) and a clock ( ) are displayed. Line buttons ( â) are aligned with the displayed lines ( ). The reception device ( ) is configured so that a user may press a line button ( â) aligned with a particular line ( ) scrolling on the display screen ( ) to view additional details related to the subject matter of the particular line ( ). Selected lines ( ) include alert activating codes ( ) which signal the reception device ( ), when enabled, to activate an alert which attracts the users attention to those selected lines ( ).

Mobile Video System

US Patent:
D505402, May 24, 2005
Filed:
Oct 3, 2003
Appl. No.:
29/191243
Inventors:
Keith K. Wong - Paradise Valley AZ, US
International Classification:
1403
US Classification:
D14125, D14126

Method For Selective Electroplating Of Semiconductor Device I/O Pads Using A Titanium-Tungsten Seed Layer

US Patent:
7144490, Dec 5, 2006
Filed:
Nov 18, 2003
Appl. No.:
10/707047
Inventors:
Tien-Jen Cheng - Bedford NY, US
David E. Eichstadt - North Salem NY, US
Jonathan H. Griffith - Lagrangeville NY, US
Sarah H. Knickerbocker - Hopewell Junction NY, US
Rosemary A. Previti-Kelly - Burlington VT, US
Roger A. Quon - Rhinebeck NY, US
Kamalesh K. Srivastava - Wappingers Falls NY, US
Keith Kwong-Hon Wong - Wappingers Falls NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
C25D 5/02
C25D 7/12
US Classification:
205118, 205122, 205123, 205136, 205157
Abstract:
A method for selective electroplating of a semiconductor input/output (I/O) pad includes forming a titanium-tungsten (TiW) layer over a passivation layer on a semiconductor substrate, the TiW layer further extending into an opening formed in the passivation layer for exposing the I/O pad, such that the TiW layer covers sidewalls of the opening and a top surface of the I/O pad. A seed layer is formed over the TiW layer, and portions of the seed layer are selectively removed such that remaining seed layer material corresponds to a desired location of interconnect metallurgy for the I/O pad. At least one metal layer is electroplated over the remaining seed layer material, using the TiW layer as a conductive electroplating medium.

Method For Fabricating Ultra High-Resistive Conductors In Semiconductor Devices And Devices Fabricated

US Patent:
2002012, Sep 12, 2002
Filed:
Jan 12, 2001
Appl. No.:
09/760240
Inventors:
Cyril Cabral - Ossining NY, US
Lawrence Clevenger - LaGrangeville NY, US
Louis Hsu - Fishkill NY, US
Keith Wong - Wappingers Falls NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01C001/012
US Classification:
338/308000, 338/307000, 338/309000
Abstract:
A high density resistor structure and a method for forming the structure are disclosed. The high density resistor structure can be constructed by an electrically insulative substrate; a refractory metal-silicon-nitrogen layer deposited on the top surface; and at least one resistor element patterned in the refractory metal-silicon-nitrogen layer in a plane parallel to the top surface. The method can be carried out by first providing the electrically insulative semiconductor substrate or a glass substrate, then sputter-depositing a TaSiN layer having a thickness between 200 and 2000 on top of the substrate; and then forming by a reactive ion etching technique at least one resistor element in the TaSiN film in a plane that is parallel to the top surface of the substrate.

Semiconductor Device Incorporating Elements Formed Of Refractory Metal-Silicon-Nitrogen And Method For Fabrication

US Patent:
2002013, Sep 19, 2002
Filed:
Jan 12, 2001
Appl. No.:
09/760245
Inventors:
Cyril Cabral - Ossining NY, US
Lawrence Clevenger - LaGrangeville NY, US
Louis Hsu - Fishkill NY, US
Keith Wong - Wappingers Falls NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L029/94
H01L029/76
H01L031/062
H01L031/113
US Classification:
257/368000
Abstract:
A semiconductor structure that includes at least one circuit element of a fuse, a diffusion barrier or a capacitor that is formed by refractory metal-silicon-nitrogen is disclosed. A method for fabricating such semiconductor structure that includes a fuse element, a diffusion barrier, a resistor or a capacitor by a refractory metal-silicon-nitrogen material is further disclosed. A suitable refractory metal-silicon-nitrogen material to be used is TaSiN which provides a wide range of resistivity by changing the ratio of Ta:Si:N. The invention provides the benefit that the various components of diffusion barriers, fuses, capacitors and resistors may be formed by a single deposition process of a TaSiN layer, the various components are then selectively masked and treated by either heat-treating or ion-implantation to vary their resistivity selectively while keeping the other shielded elements at the same resistivity.

Method For Forming Refractory Metal-Silicon-Nitrogen Capacitors And Structures Formed

US Patent:
2002018, Dec 12, 2002
Filed:
Jun 1, 2001
Appl. No.:
09/872603
Inventors:
Cyril Cabral - Ossining NY, US
Lawrence Clevenger - LaGrangeville NY, US
Louis Hsu - Fishkill NY, US
Keith Wong - Wappingers Falls NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L029/76
H01L031/062
H01L031/113
US Classification:
257/368000
Abstract:
A method for forming a refractory metal-silicon-nitrogen capacitor in a semiconductor structure and the structure formed are described. In the method, a pre-processed semiconductor substrate is first positioned in a sputtering chamber. Ar gas is then flown into the sputtering chamber to sputter deposit a first refractory metal-silicon-nitrogen layer on the substrate from a refractory metal silicide target, or from two targets of a refractory metal and a silicon. Ngas is then flown into the sputtering chamber until that the concentration of Ngas in the chamber is at least 35% to sputter deposit a second refractory metal-silicon-nitrogen layer on top of the first refractory metal-silicon-nitrogen layer. The Ngas flow is then stopped to sputter deposit a third refractory metal-silicon-nitrogen layer on top of the second refractory metal-silicon-nitrogen layer. The multi-layer stack of the refractory metal-silicon-nitrogen is then photolithographically formed into a capacitor.

Method For Forming Refractory Metal-Silicon-Nitrogen Capacitors And Structures Formed

US Patent:
2003010, Jun 12, 2003
Filed:
Jan 16, 2003
Appl. No.:
10/346437
Inventors:
Cyril Cabral - Ossining NY, US
Lawrence Clevenger - LaGrangeville NY, US
Louis Hsu - Fishkill NY, US
Keith Wong - Wappingers Falls NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L027/108
H01L029/76
US Classification:
257/306000
Abstract:
A method for forming a refractory metal-silicon-nitrogen capacitor in a semiconductor structure and the structure formed are described. In the method, a pre-processed semiconductor substrate is first positioned in a sputtering chamber. Ar gas is then flown into the sputtering chamber to sputter deposit a first refractory metal-silicon-nitrogen layer on the substrate from a refractory metal silicide target, or from two targets of a refractory metal and a silicon. Ngas is then flown into the sputtering chamber until that the concentration of Ngas in the chamber is at least 35% to sputter deposit a second refractory metal-silicon-nitrogen layer on top of the first refractory metal-silicon-nitrogen layer. The Ngas flow is then stopped to sputter deposit a third refractory metal-silicon-nitrogen layer on top of the second refractory metal-silicon-nitrogen layer. The multi-layer stack of the refractory metal-silicon-nitrogen is then photolithographically formed into a capacitor.

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