Kenneth Ying Yuen Choy, 621615 13Th St, Oakland, CA 94607

7493481, Feb 17, 2009

May 17, 2004

10/848485

Govind Kizhepat - Los Altos Hills CA, US
Kenneth Y Choy - Castro Valley CA, US
Suresh Kadiyala - Cupertino CA, US

NetXen, Inc. - Cupertino CA

G06F 9/00
G06F 7/00

712300, 712225, 712224

In some embodiments, the execution of load and store instructions for internal fields of data structures is accelerated by using on-chip template registers and appropriate machine code instructions. A load/store machine code instruction comprises an identifier of a memory address offset of an internal field word relative to a base address of the data structure, an identifier of an intra-word start bit of the internal field, and an identifier of an intra-word length of the internal field. The three identifiers may coincide, for example if the three identifiers are represented by an identity of a template register storing a template entry including the memory address offset, the start position, and the field length. The three identifiers may also be provided as part of a machine code instruction itself. Further provided are compilers, compiler methods, and hardware systems for implementing accelerated internal-field load and store operations.

8478909, Jul 2, 2013

Oct 28, 2010

12/914852

Kanoj Sarcar - Fremont CA, US
Kenneth Y. Choy - Alamo CA, US
Sanjeev Jorapur - San Jose CA, US

QLOGIC, Corporation - Aliso Viejo CA

G06F 3/00
G06F 5/00
G06F 13/28

710 26, 710 36, 710 15

Machine implemented method and system is provided. The method includes sending a packet to a device by a computing system; determining an address for the packet, where an interface logic for the device determines the address; updating a location associated with the address; where the interface logic for the device updates the location; updating a bitmap value associated with the location to indicate to a processor for the device that a location associated with the address has been updated; where the interface logic updates the bitmap value; clearing the bitmap value by writing a same value that is read by the processor for the device; and processing the packet received by the device.

6047251, Apr 4, 2000

Sep 15, 1997

8/929788

Leonard K. Pon - Los Gatos CA
Tapas Kanungo - San Jose CA
Jun Yang - Los Gatos CA
Kenneth Chan Choy - Los Gatos CA
Mindy R. Bokser - Los Gatos CA

Caere Corporation - Los Gatos CA

G06F 1728
G06K 972

704 1

The disclosed invention utilizes a dictionary-based approach to identify languages within different zones in a multi-lingual document. As a first step, a document image is segmented into various zones, regions and word tokens, using suitable geometric properties. Within each zone, the word tokens are compared to dictionaries associated with various candidate languages, and the language that exhibits the highest confidence factor is initially identified as the language of the zone. Subsequently, each zone is further split into regions. The language for each region is then identified, using the confidence factors for the words of that region. For any language determination having a low confidence value, the previously determined language of the zone is employed to assist the identification process.

6104418, Aug 15, 2000

Apr 6, 1998

9/055566

Greg L. Tanaka - Sunnyvale CA
Sean Hsi-an Kuo - Saratoga CA
Kenneth Choy - Castro Valley CA
Michael M. Lee - San Jose CA
Gregory M. Stefanek - Mountain View CA

Silicon Magic Corporation - Sunnyvale CA

G06F 1316

345521

Aspects for increasing efficiency of memory accesses during graphics rendering are provided. A preferred method aspect includes providing a plurality of memory banks for data, and decoding input signals that indicate accessing of at least one of the plurality of memory banks for a desired plurality of words of data. The method further includes splitting data access across the plurality of memory banks to allow parallel selection of an output from at least one of the plurality of memory banks as the desired plurality of words of the data, wherein latency of data access is amortized. A system aspect for improving data transfer from memory to a texture mapping unit includes a plurality of cache banks for storing texel data, a bank decode unit coupled to the plurality of cache banks for decoding a plurality of input signals indicative of selection of texel data from one or more of the plurality of banks, and selection control logic for receiving decoded address data from the bank decode unit and controlling selection of the plurality of cache banks to retrieve the texel data for output to the texture mapping unit.

5862259, Jan 19, 1999

Mar 27, 1996

8/622988

Mindy Bokser - San Francisco CA
Leonard Pon - Los Altos CA
Jun Yang - Sunnyvale CA
Kenneth Choy - San Jose CA

Caere Corporation - Los Gatos CA

G06K 962
G06K 974

382228

A pattern recognition system classifies images of patterns in which the definition of individual features of the pattern may have become blurred. The image is segmented into pieces of arbitrary size and shape, and various combinations are examined to determine those which represent the most likely segmentation of the pattern into its individual features. These individual features are then classified, according to known techniques. Through the use of a second order Markov model, not all possible combinations of pieces need to be examined, to determine the best ones. Rather, the examination of various combinations is limited in accordance with previously determined information, to thereby render the process more efficient. By combining multiple, independently determined probabilities, the accuracy of the overall operation is enhanced.

4924430, May 8, 1990

Jan 28, 1988

7/149555

John J. Zasio - Sunnyvale CA
Kenneth C. Choy - Fremont CA
Darrell R. Parham - Sunnyvale CA

Teradyne, Inc. - Boston MA

G06F 1560
G06F 1100

364578

The time verification scheme of the present invention operates without input stimulus to calculate delays along circuit paths including logic elements or cells from initial input to final output, or over sub-circuit paths, of a proposed logic design. The delay calculations include cell-dependent, and layout-dependent, and environmental-dependent factors to account for response delays on rising and falling signal; capacitance loading, temperature-dependency and voltage-dependency of a proposed logic design to provide output histograms and reports of information about overall performance, and timing violations of the proposed logic design with respect to operating parameters that can be selectively adjusted for manufacturing variations.