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Kenneth Wilson Fernald, 60511 Mandarin Flyway, Cedar Park, TX 78613

Kenneth Fernald Phones & Addresses

511 Mandarin Flyway, Cedar Park, TX 78613    512-6713850   

Sunrise Beach, TX   

Leander, TX   

Round Rock, TX   

9800 Fallon Cv, Austin, TX 78717    512-6713850   

Oak Island, NC   

Travis, TX   

Clayton, NC   

9800 Fallon Cv, Austin, TX 78717    512-6336375   

Work

Position: Sales Occupations

Education

Degree: Bachelor's degree or higher

Emails

Mentions for Kenneth Wilson Fernald

Kenneth Fernald resumes & CV records

Resumes

Kenneth Fernald Photo 13

Consultant

Location:
511 Mandarin Flyway, Cedar Park, TX 78613
Industry:
Semiconductors
Work:
Silicon Laboratories since Apr 2010
Principal Design Engineer
Keterex, Inc. Aug 2006 - Apr 2010
VP Engineering
Zilker Labs Dec 2003 - Aug 2006
CTO
Cygnal Integrated Products, Inc. Mar 1999 - Dec 2003
Senior Design Engineer
Cygnal (acquired by Silicon Labs) 1999 - 2003
Principal Engineer
Analog Devices May 1995 - Aug 1998
Senior Design Engineer
Intermedics, Inc. May 1992 - Aug 1995
Principal Design Engineer
Education:
North Carolina State University 1988 - 1992
Ph.D., Electrical Engineering
North Carolina State University 1985 - 1987
MS, Electrical Engineering
North Carolina State University 1981 - 1985
BS, Electrical Engineering
Skills:
Analog, Mixed Signal, Ic, Semiconductors, Embedded Systems, Power Management, Soc, Microcontrollers, Simulations, Electronics, System Design, Engineering, Asic, Circuit Design, Wireless, Digital Electronics, Patents, Integrated Circuits
Kenneth Fernald Photo 14

Principal Design Engineer At Silicon Laboratories

Position:
Principal Design Engineer at Silicon Laboratories
Location:
Austin, Texas Area
Industry:
Semiconductors
Work:
Silicon Laboratories since Apr 2010
Principal Design Engineer
Keterex, Inc. Aug 2006 - Apr 2010
VP Engineering
Zilker Labs Dec 2003 - Aug 2006
CTO
Cygnal Integrated Products, Inc. Mar 1999 - Dec 2003
Senior Design Engineer
Cygnal (acquired by Silicon Labs) 1999 - 2003
Principal Engineer
Analog Devices May 1995 - Aug 1998
Senior Design Engineer
Intermedics, Inc. May 1992 - Aug 1995
Principal Design Engineer
Education:
North Carolina State University 1988 - 1992
Ph.D., Electrical Engineering
North Carolina State University 1985 - 1987
MS, Electrical Engineering
North Carolina State University 1981 - 1985
BS, Electrical Engineering
Kenneth Fernald Photo 15

Kenneth Fernald

Publications & IP owners

Us Patents

Supply Voltage Monitor Using Bandgap Device Without Feedback

US Patent:
6559629, May 6, 2003
Filed:
Jul 9, 2001
Appl. No.:
09/901851
Inventors:
Kenneth W. Fernald - Austin TX
Assignee:
Cygnal Integrated Products, Inc. - Austin TX
International Classification:
G05F 316
US Classification:
323313
Abstract:
A voltage monitor having a bandgap reference circuit driven by a voltage to be monitored. The bandgap reference circuit produces a voltage and a second voltage that each vary with the voltage to be monitored. The magnitudes of these voltages are compared by an open loop comparator to provide a high speed output state. The output of the voltage monitor can be used to monitor a supply voltage and produce a reset signal to a processor if the supply voltage falls to a magnitude below a specified threshold.

Cross-Bar Matrix For Connecting Digital Resources To I/O Pins Of An Integrated Circuit

US Patent:
6738858, May 18, 2004
Filed:
May 31, 2000
Appl. No.:
09/583260
Inventors:
Kenneth W. Fernald - Austin TX
Donald E. Alfano - Round Rock TX
Assignee:
Silicon Labs CP, Inc. - Austin TX
International Classification:
G06F 1300
US Classification:
710317, 710100, 710305, 710316, 712 11, 326 41
Abstract:
A matrix of routing cells forming a cross-bar decoder ( ). Signal triplets are coupled through the cross-bar decoder ( ) based on control by a microprocessor. A register ( ) provide control signals to the cross-bar decoder ( ) to either activate or deactivate routing of the triplet signals through cells of the cross-bar decoder ( ). The routing cells are arranged in a matrix of columns and rows. Each row of cells is associated with a common data signal input, and each column of the matrix is associated with a common I/O pin. The cells are individually enabled by the microprocessor so that any data signal can be coupled to any of the I/O pins. In addition to routing data signals through the cells, other signals are also routed through the cells.

Processor Based Integrated Circuit With A Supply Voltage Monitor Using Bandgap Device Without Feedback

US Patent:
6794856, Sep 21, 2004
Filed:
May 6, 2003
Appl. No.:
10/430517
Inventors:
Kenneth W. Fernald - Austin TX
Assignee:
Silicon Labs CP, Inc. - Austin TX
International Classification:
G05F 316
US Classification:
323313
Abstract:
A voltage monitor having a bandgap reference circuit driven by a voltage to be monitored. The bandgap reference circuit produces a voltage and a second voltage that each vary with the voltage to be monitored. The magnitudes of these voltages are compared by an open loop comparator to provide a high speed output state. The output of the voltage monitor can be used to monitor a supply voltage and produce a reset signal to a processor if the supply voltage falls to a magnitude below a specified threshold.

Priority Cross-Bar Decoder

US Patent:
6839795, Jan 4, 2005
Filed:
May 31, 2000
Appl. No.:
09/584308
Inventors:
Kenneth W. Fernald - Austin TX, US
Danny J. Allred - Austin TX, US
Donald E. Alfano - Round Rock TX, US
Assignee:
Silicon Labs CP, Inc. - Austin TX
International Classification:
G06F 1300
US Classification:
710317, 710100, 710316, 710 37, 370388
Abstract:
A matrix of routing cells forming a cross-bar decoder (). Signal triplets () coupled to the cross-bar decoder () are assigned a priority. A register () provide outputs to the cross-bar decoder () to either activate or deactivate routing of the triplet signals () through the cross-bar decoder (). The routing cells () are arranged in a matrix of columns and rows, where the triplet signals are applied to the row routing cells () and are extracted at the column routing cells (). When a routing cell in a row is enabled to couple signals to an output, it disables all other lower priority routing cells in its column so that they cannot route signals to that output. Based on the automatic disabling of routing cells by others, the signals ripple through the cross-bar decoder () until all high priority I/O pins are used. The outputs of the cross-bar decoder () are coupled to respective I/O pins () by way of respective driver circuits ().

Method And Apparatus For Accessing Paged Memory With Indirect Addressing

US Patent:
6886089, Apr 26, 2005
Filed:
Nov 15, 2002
Appl. No.:
10/295585
Inventors:
Kenneth W. Fernald - Austin TX, US
Paul Highley - Austin TX, US
Brent Wilson - Austin TX, US
Assignee:
Silicon Labs CP, Inc. - Austin TX
International Classification:
G06F012/00
US Classification:
711202, 711206
Abstract:
Method and apparatus for accessing paged memory with indirect addressing. A a method for changing pages of memory in an indirect addressed memory having a plurality of addressable locations therein is diclosed. An index indicative of the page of the memory being addressed is stored in a memory location. The memory is addressed with a direct address that selects one or more of the addressable locations in the addressed page of memory. An interrupt is received from a resource capable of generating an interrupt, which interrupt has associated therewith a defined one of the pages of memory. In response to generation of the interrupt, the value of the stored index t is changed o an index associated with the defined one of the pages of memory associated with the resource. In response to receiving a signal indicative of the generated interrupt having been serviced by a system that services interrupts, the stored index is changed to a different index.

Paging Scheme For A Microcontroller For Extending Available Register Space

US Patent:
6898689, May 24, 2005
Filed:
Nov 15, 2002
Appl. No.:
10/295721
Inventors:
Kenneth W. Fernald - Austin TX, US
Paul Highley - Austin TX, US
Brent Wilson - Austin TX, US
Assignee:
Silicon Labs CP, Inc. - Austin TX
International Classification:
G06F012/00
US Classification:
711202, 711209
Abstract:
Paging scheme for a microcontroller for extending available register space. A method for paging at least a portion of an address space in a processing system is disclosed. A plurality of addressable memory locations are provided arranged in pages. Each of the addressable memory locations in each of the pages occupies at least a portion of the address space of the processing system and has an associated address in the address space of the processing system. A page pointer is stored in a storage location to define the desired page and then an address is generated in the at least a portion of the address space of the processing system. At least one of the addressable memory locations in at least two of the pages with the same address has identical information stored therein. The one of the addressable memory locations associated with both the generated address in the at least a portion of the address space in the processing system and the page pointer is then accessed.

Clock Recovery Method For Bursty Communications

US Patent:
6917658, Jul 12, 2005
Filed:
Sep 16, 2002
Appl. No.:
10/244728
Inventors:
Kenneth W. Fernald - Austin TX, US
Assignee:
Silicon Labs CP, Inc. - Austin TX
International Classification:
H04L007/00
US Classification:
375355, 375359, 375371
Abstract:
Clock recovery method for bursty communications. A method is disclosed for recovering the clock from a received data stream that comprising bursts of data with zones of substantially no data between the bursts of data. A receive clock is provided that operates within a reference frequency range. The time between data transitions in the received data is then measuring relative to the receive clock. A determination is then made if the measured time is substantially an integral of the receive clock. If not a substantial integral of the receive clock, the frequency of the receive clock is adjusted to compensate for the difference.

Method And Apparatus For Combining Outputs Of Multiple Dacs For Increased Bit Resolution

US Patent:
6950047, Sep 27, 2005
Filed:
Mar 31, 2004
Appl. No.:
10/816436
Inventors:
Douglas Piasecki - Austin TX, US
James Dub Austin - Austin TX, US
Douglas Holberg - Wimberley TX, US
Kenneth Fernald - Austin TX, US
Assignee:
Silicon Labs CP, Inc. - Austin TX
International Classification:
H03M001/20
US Classification:
341131, 341144, 341136
Abstract:
Method and apparatus for combining outputs of multiple DACs for increased bit resolution. A method for providing an increased bit resolution to a data converter operable to convert digital information to analog values. A first current Digital-to-Analog (IDAC) converter is controlled to provide current to a first output node, the first IDAC having a first current step size associated with the Least Significant Bit (LSB) thereof. A second IDAC is controlled to provide current to the first output node, the second IDAC having a second current step size associated with the LSB thereof that is smaller than the first current step size. The combination of the first and second IDACs increases the bit resolution of the first IDAC when driving the first output node with the second IDAC.

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