Kenneth Wilson Fernald, 60511 Mandarin Flyway, Cedar Park, TX 78613

6559629, May 6, 2003

Jul 9, 2001

09/901851

Kenneth W. Fernald - Austin TX

Cygnal Integrated Products, Inc. - Austin TX

G05F 316

323313

A voltage monitor having a bandgap reference circuit driven by a voltage to be monitored. The bandgap reference circuit produces a voltage and a second voltage that each vary with the voltage to be monitored. The magnitudes of these voltages are compared by an open loop comparator to provide a high speed output state. The output of the voltage monitor can be used to monitor a supply voltage and produce a reset signal to a processor if the supply voltage falls to a magnitude below a specified threshold.

6738858, May 18, 2004

May 31, 2000

09/583260

Kenneth W. Fernald - Austin TX
Donald E. Alfano - Round Rock TX

Silicon Labs CP, Inc. - Austin TX

G06F 1300

710317, 710100, 710305, 710316, 712 11, 326 41

A matrix of routing cells forming a cross-bar decoder ( ). Signal triplets are coupled through the cross-bar decoder ( ) based on control by a microprocessor. A register ( ) provide control signals to the cross-bar decoder ( ) to either activate or deactivate routing of the triplet signals through cells of the cross-bar decoder ( ). The routing cells are arranged in a matrix of columns and rows. Each row of cells is associated with a common data signal input, and each column of the matrix is associated with a common I/O pin. The cells are individually enabled by the microprocessor so that any data signal can be coupled to any of the I/O pins. In addition to routing data signals through the cells, other signals are also routed through the cells.

6794856, Sep 21, 2004

May 6, 2003

10/430517

Kenneth W. Fernald - Austin TX

Silicon Labs CP, Inc. - Austin TX

G05F 316

323313

A voltage monitor having a bandgap reference circuit driven by a voltage to be monitored. The bandgap reference circuit produces a voltage and a second voltage that each vary with the voltage to be monitored. The magnitudes of these voltages are compared by an open loop comparator to provide a high speed output state. The output of the voltage monitor can be used to monitor a supply voltage and produce a reset signal to a processor if the supply voltage falls to a magnitude below a specified threshold.

6839795, Jan 4, 2005

May 31, 2000

09/584308

Kenneth W. Fernald - Austin TX, US
Danny J. Allred - Austin TX, US
Donald E. Alfano - Round Rock TX, US

Silicon Labs CP, Inc. - Austin TX

G06F 1300

710317, 710100, 710316, 710 37, 370388

A matrix of routing cells forming a cross-bar decoder (). Signal triplets () coupled to the cross-bar decoder () are assigned a priority. A register () provide outputs to the cross-bar decoder () to either activate or deactivate routing of the triplet signals () through the cross-bar decoder (). The routing cells () are arranged in a matrix of columns and rows, where the triplet signals are applied to the row routing cells () and are extracted at the column routing cells (). When a routing cell in a row is enabled to couple signals to an output, it disables all other lower priority routing cells in its column so that they cannot route signals to that output. Based on the automatic disabling of routing cells by others, the signals ripple through the cross-bar decoder () until all high priority I/O pins are used. The outputs of the cross-bar decoder () are coupled to respective I/O pins () by way of respective driver circuits ().

6886089, Apr 26, 2005

Nov 15, 2002

10/295585

Kenneth W. Fernald - Austin TX, US
Paul Highley - Austin TX, US
Brent Wilson - Austin TX, US

Silicon Labs CP, Inc. - Austin TX

G06F012/00

711202, 711206

Method and apparatus for accessing paged memory with indirect addressing. A a method for changing pages of memory in an indirect addressed memory having a plurality of addressable locations therein is diclosed. An index indicative of the page of the memory being addressed is stored in a memory location. The memory is addressed with a direct address that selects one or more of the addressable locations in the addressed page of memory. An interrupt is received from a resource capable of generating an interrupt, which interrupt has associated therewith a defined one of the pages of memory. In response to generation of the interrupt, the value of the stored index t is changed o an index associated with the defined one of the pages of memory associated with the resource. In response to receiving a signal indicative of the generated interrupt having been serviced by a system that services interrupts, the stored index is changed to a different index.

6898689, May 24, 2005

Nov 15, 2002

10/295721

Kenneth W. Fernald - Austin TX, US
Paul Highley - Austin TX, US
Brent Wilson - Austin TX, US

Silicon Labs CP, Inc. - Austin TX

G06F012/00

711202, 711209

Paging scheme for a microcontroller for extending available register space. A method for paging at least a portion of an address space in a processing system is disclosed. A plurality of addressable memory locations are provided arranged in pages. Each of the addressable memory locations in each of the pages occupies at least a portion of the address space of the processing system and has an associated address in the address space of the processing system. A page pointer is stored in a storage location to define the desired page and then an address is generated in the at least a portion of the address space of the processing system. At least one of the addressable memory locations in at least two of the pages with the same address has identical information stored therein. The one of the addressable memory locations associated with both the generated address in the at least a portion of the address space in the processing system and the page pointer is then accessed.

6917658, Jul 12, 2005

Sep 16, 2002

10/244728

Kenneth W. Fernald - Austin TX, US

Silicon Labs CP, Inc. - Austin TX

H04L007/00

375355, 375359, 375371

Clock recovery method for bursty communications. A method is disclosed for recovering the clock from a received data stream that comprising bursts of data with zones of substantially no data between the bursts of data. A receive clock is provided that operates within a reference frequency range. The time between data transitions in the received data is then measuring relative to the receive clock. A determination is then made if the measured time is substantially an integral of the receive clock. If not a substantial integral of the receive clock, the frequency of the receive clock is adjusted to compensate for the difference.

6950047, Sep 27, 2005

Mar 31, 2004

10/816436

Douglas Piasecki - Austin TX, US
James Dub Austin - Austin TX, US
Douglas Holberg - Wimberley TX, US
Kenneth Fernald - Austin TX, US

Silicon Labs CP, Inc. - Austin TX

H03M001/20

341131, 341144, 341136

Method and apparatus for combining outputs of multiple DACs for increased bit resolution. A method for providing an increased bit resolution to a data converter operable to convert digital information to analog values. A first current Digital-to-Analog (IDAC) converter is controlled to provide current to a first output node, the first IDAC having a first current step size associated with the Least Significant Bit (LSB) thereof. A second IDAC is controlled to provide current to the first output node, the second IDAC having a second current step size associated with the LSB thereof that is smaller than the first current step size. The combination of the first and second IDACs increases the bit resolution of the first IDAC when driving the first output node with the second IDAC.