Kenneth K Ma, 601245 Maunakea St, Honolulu, HI 96817

6959395, Oct 25, 2005

Jun 26, 2002

10/180148

Kenneth Ma - Cupertino CA, US

Broadcom Corporation - Irvine CA

G06F001/26
G06F005/06
G06F001/28

713310, 713601, 713322

A method and apparatus are disclosed for conditionally enabling/disabling PCI power management in a computer-based system employing a central resource and an operating system. Non-CLKRUN# compatible PCI devices in the system are identified and whether or not the non-CLKRUN# compatible PCI devices are enabled is determined. The CLKRUN# support capability of the central resource, if available, is enabled or disabled based on, at least in part, the established status of the non-CLKRUN# compatible PCI devices. If enabled, PCI power management is provided by the CLKRUN# support capability according to the PCI CLKRUN# protocol for all CLKRUN# compatible PCI devices present in the computer-based system.

6971033, Nov 29, 2005

Jan 10, 2003

10/339843

Kenneth Ma - Cupertino CA, US

Broadcom Corporation - Irvine CA

G06F013/28

713300, 710110, 710113, 710116, 710117, 710119, 710123, 710124, 710309, 345531, 345535, 345541

A method and apparatus are disclosed for performing dynamic arbitration of memory accesses by a CPU and at least one bus master interface module based on, at least in part, monitoring a CPU throttle control signal and monitoring CPU power and performance states, and making decisions based on the monitored parameters. Bus master memory access break events and memory read and write accesses are also monitored as part of the arbitration process in accordance with certain embodiments of the present invention. An arbitration (ARB) module performs the dynamic arbitration. A CPU throttle control module generates the CPU throttle control signal, indicating when the CPU is idle, and also monitors and outputs the CPU power and performance states. A memory controller (MC) module controls accesses to the memory subsystem based on, at least in part, the dynamic arbitration performed by the dynamic arbitration module.

7010708, Mar 7, 2006

May 15, 2002

10/146554

Kenneth Ma - Cupertino CA, US

Broadcom Corporation - Irvine CA

G06F 1/32

713322, 713601

A method and apparatus are disclosed for performing adaptive run-time power management in a system employing a CPU and an operating system. A CPU cycle tracker (CCT) module monitors critical CPU signals and generates CPU performance data based on the critical CPU signals. An adaptive CPU throttler (THR) module uses the CPU performance data, along with a CPU percent idle value fed back from the operating system, to generate a CPU throttle control signal during predefined run-time segments of the CPU run time. The CPU throttle control signal links back to the CPU and adaptively adjusts CPU throttling and, therefore, power usage of the CPU during each of the run-time segments.

7028200, Apr 11, 2006

Jun 5, 2002

10/163746

Kenneth Ma - Cupertino CA, US

Broadcom Corporation - Irvine CA

G06F 1/32

713324, 713320

A method and apparatus are disclosed for performing adaptive memory power management in a system employing a CPU and a memory subsystem. A CPU throttle control (THR) module generates a CPU throttle control signal indicating when the CPU is idle. A memory controller (MC) module generates memory power management signals based on at least one of the CPU throttle control signal, memory read/write signals, memory access break events, and bus master access requests. Certain portions of the memory subsystem are powered down in response to the memory power management signals. Memory power management is performed on a time segment by time segment basis to achieve efficient power management of the memory subsystem during CPU run time.

7231534, Jun 12, 2007

Jul 26, 2005

11/189688

Kenneth Ma - Cupertino CA, US

Broadcom Corporation - Irvine CA

G06F 1/26

713323, 713300, 713310, 713320, 713321, 713322, 713324, 713330, 713340

A method and apparatus are disclosed for performing dynamic arbitration of memory accesses by a CPU and at least one bus master interface module based on, at least in part, monitoring a CPU throttle control signal and monitoring CPU power and performance states, and making decisions based on the monitored parameters. Bus master memory access break events and memory read and write accesses are also monitored as part of the arbitration process in accordance with certain embodiments of the present invention. An arbitration (ARB) module performs the dynamic arbitration. A CPU throttle control module generates the CPU throttle control signal, indicating when the CPU is idle, and also monitors and outputs the CPU power and performance states. A memory controller (MC) module controls accesses to the memory subsystem based on, at least in part, the dynamic arbitration performed by the dynamic arbitration module.

7415115, Aug 19, 2008

May 14, 2003

10/437532

Kenneth Ma - Cupertino CA, US

Broadcom Corporation - Irvine CA

H04L 9/00
H04K 1/00
G06F 11/30
G06F 3/023
G06F 21/00
H03M 11/10
H03M 11/12
H04L 9/08

380286, 380 30, 380277, 713193

Aspects of the invention provide a method and system for securely managing the storage and retrieval of data. Securely managing the storage and retrieval of data may include receiving a first disaster recovery code and acquiring a first password corresponding to the first disaster recovery code. A first disaster recovery key may be generated based on the first disaster recovery code and the first password. Another aspect of the invention may also include generating the received first disaster recovery code based on said first password and the first disaster recovery key. The generated disaster recovery code may be securely stored on at least a portion of a storage device or a removable media. Data stored on the storage device may be encrypted using the first generated disaster recovery key. Additionally, data read from the storage device may be decrypted using the generated first disaster recovery key.

7506192, Mar 17, 2009

Jan 5, 2006

11/326055

Kenneth Ma - Cupertino CA, US

Broadcom Corporation - Irvine CA

G06F 1/32

713324, 713320, 713323

A method and apparatus are disclosed for performing adaptive memory power management in a system employing a CPU and a memory subsystem. A CPU throttle control (THR) module generates a CPU throttle control signal indicating when the CPU is idle. A memory controller (MC) module generates memory power management signals based on at least one of the CPU throttle control signal, memory read/write signals, memory access break events, and bus master access requests. Certain portions of the memory subsystem are powered down in response to the memory power management signals. Memory power management is performed on a time segment by time segment basis to achieve efficient power management of the memory subsystem during CPU run time.

7523324, Apr 21, 2009

May 7, 2007

11/745047

Kenneth Ma - Cupertino CA, US

Broadcom Corporation - Irvine CA

G06F 13/28

713300, 710110, 710113, 710116, 710117, 710119, 710123, 710124, 345535, 345541

A method and apparatus are disclosed for performing dynamic arbitration of memory accesses by a CPU and at least one bus master interface module based on, at least in part, monitoring a CPU throttle control signal and monitoring CPU power and performance states, and making decisions based on the monitored parameters. Bus master memory access break events and memory read and write accesses are also monitored as part of the arbitration process in accordance with certain embodiments of the present invention. An arbitration (ARB) module performs the dynamic arbitration. A CPU throttle control module generates the CPU throttle control signal, indicating when the CPU is idle, and also monitors and outputs the CPU power and performance states. A memory controller (MC) module controls accesses to the memory subsystem based on, at least in part, the dynamic arbitration performed by the dynamic arbitration module.