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Kenneth M Ring, 532735 Matera Ln, San Diego, CA 92108

Known as:
Ken M Ring
Related to:
Katherine A Ring 60

Kenneth Ring Phones & Addresses

2735 Matera Ln, San Diego, CA 92108   

Perrysburg, OH   

7637 Royal Timbers Ln, Waterville, OH 43566    419-4412326   

Tustin, CA   

Irvine, CA   

Lucas, OH   

La Jolla, CA   

La Mesa, CA   

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Kenneth Ring Photo 32

Kenneth Ring

Location:
US Military Posts in the Pacific
Industry:
Information Technology and Services
Kenneth Ring Photo 33

Associate At Associate

Location:
Toledo, Ohio Area
Industry:
Electrical/Electronic Manufacturing

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Wikipedia

Kenneth Ring Photo 34

Kenneth Ring

Kenneth Ring (born 1936) is Professor Emeritus of psychology at the University of Connecticut, and a researcher within the field of near-death studies. ...

Us Patents

Method For Integrating Sige Npn And Vertical Pnp Devices On A Substrate And Related Structure

US Patent:
6933202, Aug 23, 2005
Filed:
Apr 9, 2004
Appl. No.:
10/821425
Inventors:
Paul D. Hurwitz - Irvine CA, US
Kenneth M. Ring - Tustin CA, US
Chun Hu - Irvine CA, US
Amol Kalburge - Irvine CA, US
Assignee:
Newport Fab, LLC - Newport Beach CA
International Classification:
H01L021/8228
US Classification:
438322, 438234, 438202, 438364, 438309, 257588
Abstract:
According to one exemplary embodiment, a method for forming an NPN and a vertical PNP device on a substrate comprises forming an insulating layer over an NPN region and a PNP region of the substrate. The method further comprises forming a buffer layer on the insulating layer and forming an opening in the buffer layer and the insulating layer in the NPN region, where the opening exposes the substrate. The method further comprises forming a semiconductor layer on the buffer layer and in the opening in the NPN region, where the semiconductor layer has a first portion situated in the opening and a second portion situated on the buffer layer in the PNP region. The first portion of the semiconductor layer forms a single crystal base of the NPN device and the second portion of the semiconductor layer forms a polycrystalline emitter of the vertical PNP device.

Method For Fabricating A Self-Aligned Bipolar Transistor Having Increased Manufacturability And Related Structure

US Patent:
6979626, Dec 27, 2005
Filed:
May 21, 2003
Appl. No.:
10/442449
Inventors:
Amol Kalburge - Irvine CA, US
Kevin Q. Yin - Irvine CA, US
Kenneth Ring - Tustin CA, US
Assignee:
Newport Fab, LLC - Newport Beach CA
International Classification:
H01L021/331
US Classification:
438321, 438364, 438320
Abstract:
According to one exemplary embodiment, a bipolar transistor comprises a base having a top surface. The bipolar transistor further comprises a base oxide layer situated on top surface of the base. The bipolar transistor further comprises a sacrificial post situated on the base oxide layer. The bipolar transistor further comprises a conformal layer situated over the sacrificial post and top surface of the base, where the conformal layer has a density greater than a density of the base oxide layer. The conformal layer may be, for example, HDPCVD oxide. According to this exemplary embodiment, the bipolar transistor further comprises a sacrificial planarizing layer situated over the conformal layer. The sacrificial planarizing layer has a first thickness in a first region between first and second link spacers and a second thickness in a second region outside of first and second link spacers, where the second thickness is generally greater than the first thickness.

Self-Aligned Bipolar Transistor Having Increased Manufacturability

US Patent:
7064415, Jun 20, 2006
Filed:
Nov 22, 2004
Appl. No.:
10/995769
Inventors:
Amol Kalburge - Irvine CA, US
Kevin Q. Yin - Irvine CA, US
Kenneth Ring - Tustin CA, US
Assignee:
Newport Fab LLC - Newport Beach CA
International Classification:
H01L 27/082
US Classification:
257565, 257642
Abstract:
According to one exemplary embodiment, a bipolar transistor comprises a base having a top surface. The bipolar transistor further comprises a base oxide layer situated on top surface of the base. The bipolar transistor further comprises a sacrificial post situated on base oxide layer. The bipolar transistor further comprises a conformal layer situated over the sacrificial post and top surface of the base, where the conformal layer has a density greater than a density of base oxide layer. The conformal layer may be, for example, HDPCVD oxide. According to this exemplary embodiment, the bipolar transistor further comprises a sacrificial planarizing layer situated over the conformal layer. The sacrificial planarizing layer has a first thickness in a first region between first and second link spacers and a second thickness in a second region outside of first and second link spacers, where the second thickness is generally greater than the first thickness.

Fabricating A Self-Aligned Bipolar Transistor Having Increased Manufacturability

US Patent:
7291536, Nov 6, 2007
Filed:
Jul 6, 2005
Appl. No.:
11/175720
Inventors:
Amol Kalburge - Irvine CA, US
Kevin Q. Yin - Irvine CA, US
Kenneth Ring - Tustin CA, US
Assignee:
Newport Fab, LLC - Newport Beach CA
International Classification:
H01L 21/8222
H01L 27/082
US Classification:
438321, 257565
Abstract:
According to one exemplary embodiment, a bipolar transistor comprises a base having a top surface. The bipolar transistor further comprises a base oxide layer situated on top surface of the base. The bipolar transistor further comprises a sacrificial post situated on base oxide layer. The bipolar transistor further comprises a conformal layer situated over the sacrificial post and top surface of the base, where the conformal layer has a density greater than a density of base oxide layer. The conformal layer may be, for example, HDPCVD oxide. According to this exemplary embodiment, the bipolar transistor further comprises a sacrificial planarizing layer situated over the conformal layer. The sacrificial planarizing layer has a first thickness in a first region between first and second link spacers and a second thickness in a second region outside of first and second link spacers, where the second thickness is generally greater than the first thickness.

Integration Of Sige Npn And Vertical Pnp Devices On A Substrate

US Patent:
7541231, Jun 2, 2009
Filed:
Mar 17, 2005
Appl. No.:
11/084391
Inventors:
Paul D. Hurwitz - Irvine CA, US
Kenneth M. Ring - Tustin CA, US
Chun Hu - Irvine CA, US
Amol Kalburge - Irvine CA, US
Assignee:
Newport Fab, LLC - Newport Beach CA
International Classification:
H01L 21/338
H01L 31/0328
H01L 31/0336
H01L 31/072
H01L 31/109
US Classification:
438170, 257197, 257565, 257552
Abstract:
According to one exemplary embodiment, a method for forming an NPN and a vertical PNP device on a substrate comprises forming an insulating layer over an NPN region and a PNP region of the substrate. The method further comprises forming a buffer layer on the insulating layer and forming an opening in the buffer layer and the insulating layer in the NPN region, where the opening exposes the substrate. The method further comprises forming a semiconductor layer on the buffer layer and in the opening in the NPN region, where the semiconductor layer has a first portion situated in the opening and a second portion situated on the buffer layer in the PNP region. The first portion of the semiconductor layer forms a single crystal base of the NPN device and the second portion of the semiconductor layer forms a polycrystalline emitter of the vertical PNP device.

Method For Integrating Sige Npn And Vertical Pnp Devices

US Patent:
7863148, Jan 4, 2011
Filed:
Apr 10, 2009
Appl. No.:
12/384937
Inventors:
Paul D. Hurwitz - Irvine CA, US
Kenneth M. Ring - Tustin CA, US
Chun Hu - Irvine CA, US
Amol M Kalburge - Irvine CA, US
Assignee:
Newport Fab, LLC - Newport Beach CA
International Classification:
H01L 21/8228
H01L 21/331
H01L 21/8222
H01L 21/8238
US Classification:
438322, 438199, 438207, 438309
Abstract:
According to one exemplary embodiment, a method for forming an NPN and a vertical PNP device on a substrate comprises forming an insulating layer over an NPN region and a PNP region of the substrate. The method further comprises forming a buffer layer on the insulating layer and forming an opening in the buffer layer and the insulating layer in the NPN region, where the opening exposes the substrate. The method further comprises forming a semiconductor layer on the buffer layer and in the opening in the NPN region, where the semiconductor layer has a first portion situated in the opening and a second portion situated on the buffer layer in the PNP region. The first portion of the semiconductor layer forms a single crystal base of the NPN device and the second portion of the semiconductor layer forms a polycrystalline emitter of the vertical PNP device.

Photovoltaic Device

US Patent:
8497151, Jul 30, 2013
Filed:
Feb 22, 2010
Appl. No.:
12/709858
Inventors:
Gang Xiong - Perrysburg OH, US
Ricky C. Powell - Ann Arbor MI, US
Aaron Roggelin - Millbury OH, US
Kuntal Kumar - Sylvania OH, US
Arnold Allenic - Ann Arbor MI, US
Kenneth M. Ring - Waterville OH, US
Charles Wickersham - Columbus OH, US
Assignee:
First Solar, Inc. - Perrysburg OH
International Classification:
H01L 21/00
US Classification:
438 57, 257E25009
Abstract:
A method to improve CdTe-based photovoltaic device efficiency is disclosed. The CdTe-based photovoltaic device can include oxygen or silicon in semiconductor layers.

Method For Fabricating A Mim Capacitor Having Increased Capacitance Density And Related Structure

US Patent:
7268038, Sep 11, 2007
Filed:
Nov 23, 2004
Appl. No.:
10/997638
Inventors:
Dieter Dornisch - Carlsbad CA, US
Kenneth M. Ring - Tustin CA, US
Tinghao F. Wang - Irvine CA, US
David Howard - Irvine CA, US
Guangming Li - Irvine CA, US
Assignee:
Newport Fab, LLC - Newport Beach CA
International Classification:
H01L 21/8242
US Classification:
438250, 257303, 257E21351, 438240, 438396
Abstract:
According to one embodiment of the invention, a method for fabricating a MIM capacitor in a semiconductor die includes a step of depositing a first interconnect metal layer. The method further includes depositing a layer of silicon nitride on the first interconnect layer. The layer of silicon nitride is deposited in a deposition process using an ammonia-to-silane ratio of at least 12. 5. The method further includes depositing a layer of MIM capacitor metal on the layer of silicon nitride. The method further includes etching the layer of MIM capacitor metal to form an upper electrode of the MIM capacitor. According to this exemplary embodiment, the method further includes etching the layer of silicon nitride to form a MIM capacitor dielectric segment and etching the first interconnect metal layer to form a lower electrode of the MIM capacitor. The MIM capacitor has a capacitance density of at least 2. 0 fF/um.

Isbn (Books And Publications)

On The Other Side Of Life : Exploring The Phenomenon Of The Near-Death Experience

Author:
Kenneth Ring
ISBN #:
0306455617

Lessons From The Light: What We Can Learn From The Near-Death Experience

Author:
Kenneth Ring
ISBN #:
0306459833

Life At Death: A Scientific Investigation Of The Near-Death Experience

Author:
Kenneth Ring
ISBN #:
0688012531

Heading Toward Omega: In Search Of The Meaning Of The Near-Death Experience

Author:
Kenneth Ring
ISBN #:
0688039103

Heading Toward Omega : In Search Of The Meaning Of The Near-Death Experience

Author:
Kenneth Ring
ISBN #:
0688062687

The Omega Project: Near-Death Experiences, Ufo Encounters, And Mind At Large

Author:
Kenneth Ring
ISBN #:
0688128467

Life At Death

Author:
Kenneth Ring
ISBN #:
0698110323

Psychological Perspective On Camille Saint-Saens

Author:
Kenneth Ring
ISBN #:
0773471081

Possible Relatives

David B Ring  Dayna R Ring  Debra A Ring  Daniel E Ring  Aaron K Ring  Denise D Ring  Danny C Ring  Kenneth L Johnson  Kenneth Stanard  Kenneth D Stancil 

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