Kent Ladia Chang, 492404 Craftsman St, Turlock, CA 95380

6355522, Mar 12, 2002

Mar 5, 1999

09/263699

Kent Kuohua Chang - Cupertino CA
John Jianshi Wang - San Jose CA
Yuesong He - San Jose CA

Advanced Micro Devices, Inc. - Sunnyvale CA

H01L 21336

438257, 438261, 257344

In one embodiment, the present invention relates to a method of forming a flash memory cell, involving the steps of forming a tunnel oxide on a substrate; forming a first polysilicon layer over the tunnel oxide by chemical vapor deposition using a silicon containing gas and a mixture of a phosphorus containing gas and a carrier gas, the first polysilicon layer having a thickness from about 800 to about 1,000 ; forming an insulating layer over the first polysilicon layer, the insulating layer comprising a first oxide layer over the first polysilicon layer, a nitride layer over the first oxide layer, and a second oxide layer over the nitride layer; forming a second polysilicon layer over the insulating layer; forming a tungsten silicide layer over the second polysilicon layer by chemical vapor deposition using WF and SiH Cl ; etching at least the first polysilicon layer, the second polysilicon layer, the insulating layer, and the tungsten silicide layer thereby defining at least one stacked gate structure; and forming a source region and a drain region in the substrate, thereby forming at least one memory cell.

6362049, Mar 26, 2002

Nov 5, 1999

09/435213

Salvatore F. Cagnina - Los Altos CA
Hao Fang - Cupertino CA
John Jianshi Wang - San Jose CA
Kent Kuohua Chang - Cupertino CA

Advanced Micro Devices, Inc. - Sunnyvale CA

H01L 21336

438258, 257315, 36518533

A semiconductor process for fabricating NAND type flash memory devices in a first embodiment includes step which can be performed on a production line which manufactures NOR type flash memory products. A NAND flash memory fabrication process according to a second embodiment simplifies the process and uses fewer masks, thus reducing costs and errors to produce higher yields.

6376309, Apr 23, 2002

Mar 16, 2001

09/811288

John JianShi Wang - San Jose CA
Kent Kuohua Chang - Cupertino CA
Hao Fang - Cupertino CA
Lu You - Santa Clara CA

Advanced Micro Devices, Inc. - Sunnyvale CA

H01L 29788

438261, 438591, 438594

The present invention provides a method for reducing the gate aspect ratio of a flash memory device. The method includes forming a tunnel oxide layer on a substrate; forming a polysilicon layer on the tunnel oxide layer; forming an insulating layer on the polysilicon layer; forming a control gate layer on the polysilicon layer; etching at least the tunnel oxide layer, the insulating layer, and the control gate layer to form at least two stack structures; forming a plurality of spacers at sides of the at least two stack structures; and filling at least one gap between the at least two stack structures with an oxide, where the control gate layer provides a gate aspect ratio which allows for a maximum step coverage by the oxide. In a preferred embodiment, the method uses nickel silicide instead of the conventional tungsten silicide in the control gate layers of the cells of the device. Nickel silicide has higher conductivity than conventional silicides, thus a thinner layer of nickel silicide may be used without sacrificing performance.

6380029, Apr 30, 2002

Dec 4, 1998

09/205899

Kent Kuohua Chang - Cupertino CA
Kenneth Wo-Wai Au - Fremont CA
John Jianshi Wang - San Jose CA

Advanced Micro Devices, Inc. - Sunnyvale CA

H01L 21330

438257, 438261

In one embodiment, the present invention relates to a method of forming a flash memory cell, involving the steps of forming a tunnel oxide on a substrate; forming a first polysilicon layer over the tunnel oxide; forming an insulating layer over the first polysilicon layer, the insulating layer comprising a first oxide layer over the first polysilicon layer, a nitride layer over the first oxide layer, and a second oxide layer over the nitride layer; forming a second polysilicon layer over the insulating layer; forming a tungsten silicide layer over the second polysilicon layer by chemical vapor deposition using WF and SiH Cl ; etching at least the first polysilicon layer, the second polysilicon layer, the insulating layer, and the tungsten silicide layer thereby defining at least one stacked gate structure; and forming a source region and a drain region in the substrate, thereby forming at least one memory cell.

6380033, Apr 30, 2002

Sep 20, 1999

09/399414

Kent K. Chang - Cupertino CA
Allen U. Huang - San Jose CA

Advanced Micro Devices, Inc. - Sunnyvale CA

H01L 21336

438258, 438264, 438594, 438770

In one embodiment, the present invention relates to a method of forming a NAND type flash memory device capable of more than about 1Ã10 program/erase cycles without significant read disturb problems involving the steps of growing a first oxide layer over at least a portion of a substrate, the substrate including a flash memory cell area and a select gate area; removing a portion of the first oxide layer in the flash memory cell area of the substrate; growing a second oxide layer over at least a portion of the substrate in the flash memory cell area and over at least a portion of the a first oxide layer in the select gate area; annealing the first oxide layer and the second oxide layer under an inert gas and at least one of N O and NO for a period of time from about 1 minute to about 15 minutes; depositing a first in situ doped amorphous silicon layer over at least a portion of the second oxide layer; depositing a dielectric layer over at least a portion of the first in situ doped amorphous silicon layer; depositing a second doped amorphous silicon layer over at least a portion of the dielectric layer; and forming a flash memory cell in the flash memory cell area of the substrate and a select gate transistor in the select gate area substrate, the flash memory cell comprising the second oxide layer, the first in situ doped amorphous silicon layer, the dielectric layer, and the second doped amorphous silicon layer, and the select gate transistor comprising the first oxide layer, the second oxide layer, the first in situ doped amorphous silicon layer, the dielectric layer, and the second doped amorphous silicon layer.

6410949, Jun 25, 2002

Jan 31, 2001

09/774327

John JianShi Wang - San Jose CA
Kent Kuohua Chang - Cupertino CA
Hao Fang - Cupertino CA

Advanced Micro Devices, Inc. - Sunnyvale CA

H01L 218242

257252, 257315, 257316

The present invention provides a method for monitoring for a second gate over etch in a flash memory device. The method includes providing at least one select transistor stack structure in the core area of the substrate and at least one monitor structure in the monitor area of the substrate; determining a thickness of a select gate layer of the at least one monitor structure; and determining if a second gate over etch occurred upon the thickness of the select gate layer of the at least one monitor structure. The select gate layer of the monitor structure is the same select gate layer of the select transistor stack structure. The select gate thickness of the select transistor stack structure may be determined by measuring the thickness at the monitor structure. This measurement is possible at the monitor area because the monitor structures are placed far enough apart to support measuring instruments. With the method in accordance with the present invention, a second gate over etch and its extent can be monitored without destroying the device.

6458212, Oct 1, 2002

Mar 31, 2000

09/539393

Fuodoor Gologhlan - Campbell CA
David Chi - Sunnyvale CA
Kent Kuohua Chang - Cupertino CA
Hector Serrato - Ceres CA
Jayendra Bhakta - Sunnyvale CA

Advanced Micro Devices, Inc. - Sunnyvale CA

C23C 1600

118715, 553852, 55463, 55521, 55487, 55486, 55525, 55DIG 30

One aspect of the present invention relates to a tetraethylorthosilicate chemical vapor deposition method, involving the steps of forming a film on a substrate using tetraethylorthosilicate in a chemical vapor deposition chamber; and removing tetraethylorthosilicate byproducts from the chemical vapor deposition chamber via a pump system and an exhaust line connected to the chemical vapor deposition chamber, the exhaust line comprising a mesh filter having a conical shape. Another aspect of the present invention relates to an exhaust system for removing tetraethylorthosilicate byproducts from a chemical vapor deposition chamber, containing an exhaust line connected to the chemical vapor deposition chamber, the exhaust line comprising a mesh filter having a conical shape via a pump system; and a pump system connected to the exhaust line for removing tetraethylorthosilicate byproducts from the processing chamber.

6498104, Dec 24, 2002

Feb 2, 2001

09/776308

Fuodoor Gologhlan - Campell CA
David Chi - Sunnyvale CA
Kent Kuohua Chang - Cupertino CA
Hector Serrato - Ceres CA

Advanced Micro Devices, Inc. - Sunnyvale CA

H01L 21311

438695, 438257, 134 1, 134 13, 118715, 118719

In one embodiment, the present invention relates to a method of cleaning a low pressure chemical vapor deposition apparatus having TEOS material build-up therein involving contacting the low pressure chemical vapor deposition apparatus with a composition containing at least one lower alcohol. In another embodiment, the present invention relates to a system for cleaning a low pressure chemical vapor deposition apparatus having TEOS material build-up therein, containing a supply of a composition comprising at least one lower alcohol; an injection port for introducing the composition including at least one lower alcohol into the low pressure chemical vapor deposition apparatus; and a pump/vacuum system for removing crystallized TEOS material build-up from the low pressure chemical vapor deposition apparatus.