Kerry GloverGarland, TX

6567489, May 20, 2003

Feb 8, 1999

09/246408

Kerry C. Glover - Wylie TX

Texas Instruments Incorporated - Dallas TX

H03D 324

375376, 375345, 375229

A method for acquiring a signal in a read channel ( ), the read channel ( ) having an equalizer ( ), includes performing an automatic gain control sequence; performing a phase locked loop sequence that includes performing a fast phase locked loop step, the fast phase locked loop step including bypassing the equalizer; and performing a synchronization search sequence.

2007024, Oct 25, 2007

Apr 25, 2006

11/410394

Kerry Glover - Rockwall TX, US
Edgar Zuniga-Ortiz - McKinney TX, US

H01L 23/34

257706000, 257E23110

A heatsink architecture employing a combination of stiffeners and flex substrate to improve the sinking of heat from the integrated circuit. The stiffener may be employed in numerous locations, including above the integrated circuit, or interposed between the integrated circuit and an e-block. The flex substrate may be interposed between the integrated circuit and the stiffener, while in other embodiments the integrated circuit is directly coupled to the e-block via heat conductive epoxy and the like. Solder balls may be employed to connect the flex substrate to integrated circuit. The flex substrate may take different forms, and may or may not be connected to the e-block. The flex substrate may be connected directly to the e-block, or connected via an e-pin extending through layers including the flex substrate and/or the stiffener.

2013017, Jul 11, 2013

Jan 9, 2013

13/737850

ams AG - Unterpremstatten, AT
David Mehrl - Plano TX, US
Greg Stoltz - Flower Mound TX, US
Kerry Glover - Rockwall TX, US

ams AG - Unterpremstatten

G01J 3/28
G02B 27/42

356326, 359558

A dispersive element is disclosed which is designed to receive incident light () and disperse the incident light () into multiple spatially separated wavelengths of light. The dispersive body (DB) comprises a collimation cavity (COLL) to collimate the incident light (), at least two optical interfaces (PRIS) to receive and disperse the collimated light () and a collection cavity (CLCT) to collect the dispersed light () from the at least two dispersive interfaces (op op) and to focus the collected light ().

6151178, Nov 21, 2000

Mar 18, 1997

8/819064

Kerry C. Glover - Wylie TX

Texas Instruments Incorporated - Dallas TX

G11B 509
G11B 5035

360 46

A read channel (18) is provided for use in a mass storage system. The read channel (18) includes a plurality of circuit modules and an error estimation circuit (50). The plurality of circuit modules receive an analog data signal from a disk/head assembly (12) and condition the signal to provide a digital data signal. The error estimation circuit (50) receives an analog signal from one of the plurality of circuit modules and analyzes the analog signal. The error estimation circuit (50) provides digital error signal (94) and digital level estimation signal (96) as a result.

6032171, Feb 29, 2000

Jan 4, 1995

8/368680

Sami Kiriaki - Garland TX
Kerry C. Glover - Wylie TX

Texas Instruments Incorporated - Dallas TX

G06G 702
G06F 1710

708819

A novel Finite Impulse Response ("FIR") filter (10)" is provided with precise timing acquisition. A master/slave sample and hold architecture is employed. In this architecture, an input signal (VIN) is coupled to an input of a master sample and hold circuit (34). A plurality of slave sample and hold circuits (36-44) are coupled to the output of the master sample and hold circuit. The outputs of the slave sample and hold circuits (36-44) are multiplexed to a plurality of multipliers (14-22) in a round robin manner.

6018554, Jan 25, 2000

Apr 24, 1997

8/840649

Kerry C. Glover - Wylie TX

Texas Instruments Incorporated - Dallas TX

H04L 2708

375345

An automatic gain control circuit (44) is provided for generating an output gain signal (64) in a control loop. The control loop may a continuous-time control loop or a sampled-time control loop. The automatic gain control circuit (144) includes a gain control circuit (100), an amplifier circuit such as a first amplifier (120) or a second amplifier (122), a control circuit (126), and a low pass filter (84). The gain control circuit (144) receives a read signal and generates an error signal in response. The first amplifier (120) receives the error signal and generates an amplified error signal. The control circuit (126) controls various switches, such as a first switch (100) and a second switch (102), so that the amplified error signal and the error signal may be provided to the low pass filter (84) during different periods. The amplified error signal is provided during a first period that is shorter than the response time of the control loop. The error signal is provided next after the first period and after a second period that is longer than the response time of the control loop.

5978426, Nov 2, 1999

Apr 16, 1997

8/834413

Kerry C. Glover - Wylie TX
Benjamin J. Sheahan - Dallas TX

Texas Instruments Incorporated - Dallas TX

H03D 324

375376

A phase locked loop system (52) and method is used in a synchronously sampled data channel (10) of a disk drive mass storage system (30).

5829011, Oct 27, 1998

Jan 31, 1997

8/797679

Kerry C. Glover - Wylie TX

Texas Instruments Incorporated - Dallas TX

G06F 1200

711100

An electronic circuit used in the control and operation of a mass storage system (30) is provided that includes an SSD channel (10), and a control circuitry (11) having a microprocessor (28) and a read only memory (ROM) (29). During an initialization routine, microprocessor (28) and the ROM (29) of the control circuitry (11) provide operational parameters to the SSD channel (10) through a data/parameter path (13). The SSD channel (10) receives these operational parameters and stores them in a parameter memory (22) so that a read channel (18) may access the operational parameters during read operations. During read operations, the read channel (18) receives a stored data signal from a disk/head assembly (12) and a preamplifier (14). The read channel (18) processes the stored data signal and provides an output digital data signal. The digital data signal is provided to the control circuitry (11) through the data/parameter path (13).