Kerry Tedrow resumes & CV records
Resumes
Kerry D Tedrow, 641261 Humbug Creek Ct, Folsom, CA 95630
Kerry Tedrow Phones & Addresses
1261 Humbug Creek Ct, Folsom, CA 95630 916-9849680
124 Amaya Dr, Folsom, CA 95630
107 Loughridge Way, Folsom, CA 95630
608 Mormon St, Folsom, CA 95630
6120 Rich Hill Dr, Orangevale, CA 95662 916-9887705
Sacramento, CA
1261 Humbug Creek Ct, Folsom, CA 95630
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Sales Occupations
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Degree:
Graduate or professional degree
Mentions for Kerry D Tedrow
Publications & IP owners
Us Patents
Oscillator For Simultaneously Generating Multiple Clock Signals Of Different Frequencies
US Patent:
6359809, Mar 19, 2002
Filed:
Dec 10, 1997
Appl. No.:
08/988225
Inventors:
Kerry D. Tedrow - Folsom CA
Jeffrey J. Evertt - Folsom CA
Jeffrey J. Evertt - Folsom CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G11C 1604
US Classification:
36518529, 36518909, 365233
Abstract:
A low frequency oscillator is described. The low frequency oscillator has a bias circuit including a metal-oxide semiconductor (MOS) resistor. A biased ring oscillator is coupled to the bias circuit. The biased ring oscillator includes multiple current limiting transistors.
Negative Output Voltage Charge Pump And Method Therefor
US Patent:
6359814, Mar 19, 2002
Filed:
Dec 29, 2000
Appl. No.:
09/753351
Inventors:
Rajesh Sundaram - Fair Oaks CA
Kerry D. Tedrow - Folsom CA
Kerry D. Tedrow - Folsom CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G11C 700
US Classification:
36518909, 36518911, 327535, 331 17
Abstract:
A negative voltage charge pump including a regulation circuit. The regulation circuit has a level shift ladder including a plurality of level shifters connected in series. One end of the level shift ladder receives a power supply voltage and the other end receives the negative output of the charge pump. A feedback voltage is generated from one of the intermediate nodes of the level shift ladder. A differential amplifier generates a regulation voltage which varies as a function of the feedback voltage and a reference voltage. The regulation voltage is applied to a frequency control input of a voltage-controlled oscillator for generating a signal that drives the charge pump. Each of the level shifters of the level shift ladder can be a triple well device that can be configured to handle negative voltages without forward biasing an internal p-n junction.
Oscillator For Simultaneously Generating Multiple Clock Signals Of Different Frequencies
US Patent:
6429732, Aug 6, 2002
Filed:
Oct 27, 2000
Appl. No.:
09/698965
Inventors:
Kerry D. Tedrow - Folsom CA
Jeffrey J. Evertt - Folsom CA
Jeffrey J. Evertt - Folsom CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01J 1982
US Classification:
327548, 327536, 331 57
Abstract:
A low frequency oscillator is described. The low frequency oscillator has a bias circuit including a metal-oxide semiconductor (MOS) resistor. A biased ring oscillator is coupled to the bias circuit. The biased ring oscillator includes multiple current limiting transistors.
Local Sensing Of Non-Volatile Memory
US Patent:
6477086, Nov 5, 2002
Filed:
Dec 29, 2000
Appl. No.:
09/752936
Inventors:
Ritesh Trivedi - Fair Oaks CA
Mark Bauer - Placerville CA
Sandeep Guliani - Folsom CA
Balaji Srinivasan - Fair Oaks CA
Kerry Tedrow - Folsom CA
Mark Bauer - Placerville CA
Sandeep Guliani - Folsom CA
Balaji Srinivasan - Fair Oaks CA
Kerry Tedrow - Folsom CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G11C 1606
US Classification:
36518521, 36518522, 36518511
Abstract:
According to the invention, an apparatus and method are disclosed for sensing the contents of non-volatile memory. According to one embodiment, a set of local sensing circuits is used to read the logical values stored in memory cells contained within a partition of a non-volatile memory device.
Method, Apparatus, And System To Enhance Negative Voltage Switching
US Patent:
6477091, Nov 5, 2002
Filed:
Mar 30, 2001
Appl. No.:
09/823463
Inventors:
Kerry D. Tedrow - Folsom CA
Rajesh Sundaram - Fair Oaks CA
Rajesh Sundaram - Fair Oaks CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G11C 700
US Classification:
36518911, 36518518, 36518529
Abstract:
The present invention is in the field of flash memory. More particularly, embodiments of the present invention may provide a negative voltage for erasing when coupled to a memory cell to be erased and provide voltages to read or program when not coupled to a memory cell that is selected to be erased. Embodiments may also provide a high magnitude negative voltage to erase; a low impedance, low voltage current to read or program; and burn little to no current when not coupled to a memory cell that is selected to be erased.
Charging A Capacitance Of A Memory Cell And Charger
US Patent:
6504760, Jan 7, 2003
Filed:
Jun 22, 2001
Appl. No.:
09/888252
Inventors:
Kerry D. Tedrow - Folsom CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G11C 1604
US Classification:
36518519, 36518524, 36518528, 36518529
Abstract:
The present invention is in the field of charging a capacitance of a memory cell. Embodiments of the present invention program a memory cell by determining programming pulses to be used to program the memory cell based on a target state and the memory cells response to previous program pulses.
Method And Apparatus For Matched-Reference Sensing Architecture For Non-Volatile Memories
US Patent:
6515906, Feb 4, 2003
Filed:
Dec 28, 2000
Appl. No.:
09/752714
Inventors:
Kerry D. Tedrow - Folsom CA
Balaji Srinivasan - Fair Oaks CA
Owen W. Jungroth - Sonora CA
Balaji Srinivasan - Fair Oaks CA
Owen W. Jungroth - Sonora CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G11C 1606
US Classification:
36518521, 36518511
Abstract:
According to one aspect of the present invention, an apparatus is provided that includes a first global bit line, a second global bit line, a first block, a second block, and a reference cell array. The first block contains a first local bit line and a plurality of memory cells coupled to the first local bit line. The first local bit line can be selectively coupled to the first global bit line based upon a first control input. The second block contains a second local bit line and a plurality of memory cells coupled to the second local bit line. The second local bit line can be selectively coupled to the second global bit line based upon a second control input. The reference cell array contains a plurality of reference cells. The plurality of reference cells can be selectively coupled to either the first global bit line or the second global bit line based upon a third control input.
Charging A Capacitance Of A Memory Cell And Charger
US Patent:
6597606, Jul 22, 2003
Filed:
May 23, 2002
Appl. No.:
10/154019
Inventors:
Kerry D. Tedrow - Folsom CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G11C 1604
US Classification:
36518528, 36518518, 36518524
Abstract:
The present invention is in the field of charging a capacitance of a memory cell. Embodiments of the present invention program a memory cell by determining programming pulses to be used to program the memory cell based on a target state and the memory cells response to previous program pulses.
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