Kevin M Mccall, 5814 Lord Jeffrey Dr, Amherst, NH 03031

5598364, Jan 28, 1997

Nov 17, 1995

8/560002

Kevin J. McCall - Leominster MA
Janos Kovacs - North Andover MA
Wyn Palmer - North Andover MA

Analog Devices, Inc. - Norwood MA

G11C 1300

365 73

A write precompensation circuit includes a plurality of current-controlled delay buffers connected to form a delay line having selectable output taps. The precise delay of each delay buffer is controllable by a secondary control current derived from a master control current such that the precise delay is a precise percent of an oscillator period. The master control current is also used to control the period of a master write clock generated by a current-controlled ring oscillator of delay buffers. A write precompensation method includes steps of controlling current in delay buffers in a current-controlled ring oscillator used to generate a master write clock and current in delay buffers in a current-controlled delay line to maintain delays through delay buffers of the oscillator and the delay line in predetermined proportions to each other.

5646968, Jul 8, 1997

Nov 17, 1995

8/560013

Janos Kovacs - Andover MA
Ronald Kroesen - Harvard MA
Kevin McCall - Leominster MA

Analog Devices, Inc. - Norwood MA

H03D 324

375375

A dynamic phase selector phase locked loop circuit includes: an A/D converter for receiving an input to be sampled; a phase detection circuit for determining the phase error between the input signal and a clock signal; a clock circuit, responsive to the phase detection circuit, for providing the clock signal to the A/D converter for timing the sampling of the input signal; the clock circuit including a delay circuit having a number of delay taps; and a phase selector circuit, responsive to the phase detection circuit, for initially gating the clock signals to the A/D converter from the clock circuit, and enabling one of the delay taps to dynamically adjust the phase of the clock signal and reduce the initial phase error.

6147531, Nov 14, 2000

Jul 9, 1998

9/112889

Kevin J. McCall - Leominster MA
Janos Kovacs - North Andover MA

Analog Devices, Inc. - Norwood MA

H03L 706

327158

A write channel in read/write disc drive system for writing data signals to a drive includes a variable delay circuit having a number of selectable taps for correcting for non-linear transition shift; and a delay locked loop circuit responsive to the data signal for controlling the delay of the variable circuit.

6144981, Nov 7, 2000

Oct 19, 1998

9/174944

Janos Kovacs - North Andover MA
Kevin J. McCall - Leominster MA

Analog Devices, Inc. - Norwood MA

G06G 702

708819

A programmable pulse slimmer system for a low pass ladder filter includes a filter input current source for providing to a low pass ladder filter the input signal to be filtered; and a high frequency boost current source for injecting into the low pass ladder filter forward of the first inductor device a high frequency load current which is a scaled inverse replica of the input signal to provide gain at the high frequency end of the low pass band of the low pass ladder filter.

5656952, Aug 12, 1997

Nov 13, 1995

8/558010

Kevin J. McCall - Leominster MA
David Reynolds - Georgetown MA

Analog Devices, Inc. - Wilmington MA

H03K 1900

326 82

According to embodiments of the present invention, a driver circuit, has first and second reference voltage rails for receiving first and second reference voltages, has first and second inputs for receiving an input differential signal and has first and second outputs for providing an output differential signal. The driver circuit comprises a first CMOS transistor, a second CMOS transistor, and first, second and third current sources. Positive voltage levels with respect to ground at the first and second outputs, are within typical acceptable ECL output voltage levels.

5793239, Aug 11, 1998

Aug 29, 1997

8/920692

Janos Kovacs - North Andover MA
Kevin McCall - Leominster MA

Analog Devices, Inc. - Norwood MA

H03H 1126

327262

A composite load circuit for use within another circuit includes at least one amplifying transistor. The composite load circuit includes first and second transistors connected in parallel. Each load transistor has a gate that receives a common control voltage. Each load transistor also has a different turn-on threshold voltage. A resistor, connected in parallel with the load transistors, limits an effective impedance of the load transistors.

5541532, Jul 30, 1996

Aug 17, 1995

8/516384

Kevin J. McCall - Leominster MA

Analog Devices, Inc. - Norwood MA

H03K 19094
H03K 190175

326 68

An all MOS single-ended to differential level converter including: first and second source follower circuits each including first and second PMOS semiconductors each having a drain, a source and a gate electrode; a current source commonly connected to the drain electrodes of the first and second PMOS semiconductors; an input circuit for providing to one of the gate electrodes a single-ended input signal and to the other an inverted single-ended input signal; and first and second load impedances connected to the source electrodes of the first and second PMOS semiconductors, respectively, for providing output analog differential signals at a level which is a function of the load impedances and current source magnitude.