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Kevin A Pasnik, 57Austin, TX

Known as:
Kevin Anthony Pasnik Kevin N Pasnik Kevin P Pasnik Kevin A Pasnic
Related to:
Diane M Barth 64

Kevin Pasnik Phones & Addresses

Austin, TX   

Johnson City, TN   

905 Timber Trl, Cedar Park, TX 78613    512-5850307   

106 San Mateo Ter, Cedar Park, TX 78613    512-2579693   

Leander, TX   

Essex Junction, VT   

Westford, VT   

Wappingers Falls, NY   

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Kevin A Pasnik

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Work

Company: Ibm 1989 to 2010 Position: Senior software engineer

Education

Degree: Bachelors, Bachelor of Science School / High School: Rochester Institute of Technology 1985 to 1990 Specialities: Applied Mathematics

Skills

Software Development • Debugging • Simulations • Perl • Computer Architecture • Functional Verification • Unix • C • Eda • Linux • Processors • High Performance Computing • Vhdl • Asic • Shell Scripting • Tcl • Verilog • Embedded Systems • Algorithms • Device Drivers • Logic Design • Hardware Architecture • System Architecture • Vlsi • Microprocessors • Team Leadership • Soc

Industries

Computer Hardware
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Kevin Pasnik resumes & CV records

Resumes

Kevin Pasnik Photo 12

Simulation Acceleration Verification, Software Development

Location:
Houston, TX
Industry:
Computer Hardware
Work:
Ibm 1989 - 2010
Senior Software Engineer Ibm 1989 - 2010
Simulation Acceleration Verification, Software Development
Education:
Rochester Institute of Technology 1985 - 1990
Bachelors, Bachelor of Science, Applied Mathematics
Skills:
Software Development, Debugging, Simulations, Perl, Computer Architecture, Functional Verification, Unix, C, Eda, Linux, Processors, High Performance Computing, Vhdl, Asic, Shell Scripting, Tcl, Verilog, Embedded Systems, Algorithms, Device Drivers, Logic Design, Hardware Architecture, System Architecture, Vlsi, Microprocessors, Team Leadership, Soc

Publications & IP owners

Us Patents

Instruction Encoding In A Hardware Simulation Accelerator

US Patent:
7865346, Jan 4, 2011
Filed:
Mar 30, 2007
Appl. No.:
11/694940
Inventors:
Gernot E. Günther - Endicott NY, US
Viktor Gyuris - Wappingers Falls NY, US
Kevin Anthony Pasnik - Cedar Park TX, US
Thomas John Tryt - Binghamton NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 17/50
G06G 7/62
H03K 19/00
US Classification:
703 13, 703 15, 716 4, 716 17
Abstract:
A hardware simulation accelerator to simulate logic designs, a method to encode instructions for use in the hardware simulation accelerator, and a computer program product having code of the method by which the hardware simulation accelerator can read encoded instructions to simulate the logic design, and computer program product of the encoded instructions to simulate a logic design in a hardware accelerator. Each instruction has one of a plurality of opcodes, the opcodes select which of the hardware resources of the hardware simulation accelerator will implement and use the values set forth in other programmable bits of the encoded instruction. The encoded instruction may be a routing and/or a gate evaluation instruction.

Hardware Simulation Accelerator Design And Method That Exploits A Parallel Structure Of User Models To Support A Larger User Model Size

US Patent:
7945433, May 17, 2011
Filed:
Apr 30, 2007
Appl. No.:
11/742100
Inventors:
Gernot E. Guenther - Endicott NY, US
Viktor Gyuris - Wappingers Falls NY, US
Harrell Hoffman - Austin TX, US
Kevin A. Pasnik - Cedar Park TX, US
Thomas J. Tryt - Binghamton NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 9/445
G06F 9/30
US Classification:
703 14, 703 26, 717140, 712 20
Abstract:
A system and method for design verification and, more particularly, a hardware simulation accelerator design and method that exploits a parallel structure of user models to support a large user model size. The method includes a computer including N number of logic evaluation units (LEUs) that share a common pool of instruction memory (IM). The computer infrastructure is operable to: partition a number of parallel operations in a netlist; and send a same instruction stream of the partitioned number of parallel operations to N number of LEUs from a single IM. The system is a hardware simulation accelerator having a computer infrastructure operable to provide a stream of instructions to multiple LEUs from a single IM. The multiple LEUs are clustered together with multiple IMs such that each LEU is configured to use instructions from any of the multiple IMs thereby allowing a same instruction stream to drive the multiple LEUs.

Possible Relatives

Diana M Pasnik  John F Pasnik  Matthew J Pasnik  Michael J Pasnik  Kevin T Johnson  Kevin Stamps  Kevin Stanberry  Kevin R Stancil  Kevin R Standage  Kevin J Standish 

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