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Kevin M Traynor, 675101 Sandy Banks Rd, Raleigh, NC 27616

Known as:
Kevin Michael Traynor Kevin T Raynor Catherine Dugan
Related to:
Donna Smith Crawford 71

Kevin Traynor Phones & Addresses

5101 Sandy Banks Rd, Raleigh, NC 27616    303-4523077   

Livingston, TX   

Richardson, TX   

Cary, NC   

Thornton, CO   

Fort Collins, CO   

Austin, TX   

Port Saint Lucie, FL   

5101 Sandy Banks Rd, Raleigh, NC 27616   

Work

Company: The blue goose inn Address: 14860 Montfort Dr., Dallas, TX 75254 Phones: 972-4581701 Position: Genaral manager Industries: Eating Places

Education

Degree: Graduate or professional degree
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Mentions for Kevin M Traynor

Career records & work history

Medicine Doctors

Kevin M. Traynor

Specialties:
Cardiovascular Disease, Internal Medicine
Work:
Kevin M Traynor MD
2697 SW Prt St Lucie Blvd, Port Saint Lucie, FL 34953
772-3350505 (phone) 772-3350508 (fax)
Education:
Medical School
Univ C.e.t.e.c., Sch of Med, Santo Domingo, Dom Rep (closed 1984)
Graduated: 1981
Procedures:
Echocardiogram
Conditions:
Cardiomyopathy, Heart Failure, Valvular Heart Disease, Acute Myocardial Infarction (AMI), Angina Pectoris, Aortic Regurgitation, Aortic Valvular Disease, Atrial Fibrillation and Atrial Flutter, Cardiac Arrhythmia, Conduction Disorders, Congenital Anomalies of the Heart, Endocarditis, Ischemic Heart Disease, Mitral Stenosis, Mitral Valvular Disease, Paroxysmal Supreventricular Tachycardia (PSVT), Pericardidtis
Languages:
English, French
Description:
Dr. Traynor graduated from the Univ C.e.t.e.c., Sch of Med, Santo Domingo, Dom Rep (closed 1984) in 1981. He works in Port Saint Lucie, FL and specializes in Cardiovascular Disease and Internal Medicine. Dr. Traynor is affiliated with Martin Medical Center and Saint Lucie Medical Center.

License Records

Kevin Edward Traynor

Licenses:
License #: RS171245L - Expired
Category: Real Estate Commission
Type: Real Estate Salesperson-Standard

Resumes & CV records

Resumes

Kevin Traynor Photo 39

Financial Services Professional At Nylife

Position:
Financial Services Professional at NYLife
Location:
Raleigh-Durham, North Carolina Area
Industry:
Financial Services
Work:
NYLife
Financial Services Professional B&S Financing - Lexington SC Dec 2003 - May 2008
Owner UPS - Columbia SC Oct 1984 - Dec 2003
Business Manager
Kevin Traynor Photo 40

Division Director At Robert Half International

Position:
Division Director at Robert Half International
Location:
Jacksonville, Florida
Industry:
Staffing and Recruiting
Work:
Robert Half International - Jacksonville, Florida Area since Sep 2011
Division Director Robert Half International Dec 2009 - Nov 2011
Staffing Manager SDI Networks Aug 2007 - May 2009
Inside Sales
Education:
Furman University 2002 - 2006
Bachelor of Arts, Political Science
Kevin Traynor Photo 41

Ic Design And Verification

Location:
Richardson, Texas
Industry:
Semiconductors
Work:
Texas Instruments - Dallas, TX Sep 2012 - Feb 2013
Contract Design and Verification Engineer Texas Instruments Oct 2011 - Apr 2012
Contract Circuit Design Engineer IBM Jan 2010 - Jul 2011
Contract Circuit Design Engineer AMD Nov 2006 - Jan 2009
Senior Member Technical Staff IBM Jan 2006 - Jul 2006
Long Term Supplemental Employee Renesas Technology America 2003 - 2005
Member Technical Staff Mitsubishi Electric Nov 1999 - Jun 2003
Member Technical Staff Motorola Semiconductor Nov 1988 - Nov 1999
Member Technical Staff
Education:
Youngstown State University 1974 - 1979
BEEE, Electrical Engineering
Skills:
VHDL, Verilog, Circuit Design, Logic Design, Simulation, CMOS, Technology Transfer, Layout, IC, VLSI, Circuit Simulators, Ultrasim, SPICE, Spectre, Verilog-A, Memory, Flash Memory, SRAM, Microcontrollers, Unix Shell Scripting, Cadence Virtuoso
Honor & Awards:
PATENTS U.S. #7,545,614 - ESD power clamp with variable on time A#20050021894 - Method and system for interrupt mapping A#20040091106 - Scrambling of data streams having arbitrary data path widths U.S. #5,872,940 - Programmable Read/Write access signal U.S. #5,502,406 - Low Power Level Shifting Circuit U.S. #5,272,453 - Method and apparatus for switching between gain curves of a VCO U.S. #4,689,792 - ROM with error detection and correction and self-testing capability U.S. #4,710,934 - RAM with error detection and correct capability PUBLICATIONS A Glueless Bus Interface For An Embedded Microprocessor - Proceedings of European Microprocessor Symposium, 1996
Kevin Traynor Photo 42

Kevin Traynor

Location:
United States

Publications & IP owners

Us Patents

Electrostatic Discharge Device With Variable On Time

US Patent:
7545614, Jun 9, 2009
Filed:
Sep 30, 2005
Appl. No.:
11/239130
Inventors:
Kevin Traynor - Cary NC, US
Russell C. Deans - Durham NC, US
Vincent J. Acierno - Chapel Hill NC, US
Assignee:
Renesas Technology America, Inc. - San Jose CA
International Classification:
H02H 9/00
US Classification:
361 56
Abstract:
Disclosed is an electrostatic discharge device, typically referred to as a power clamping circuit, for minimizing the effects of an initial ESD event as well as providing protection against subsequent ESD events. The power clamp is left fully turned on during and after an ESD event. Subsequent ESD events are those ESD events occurring shortly after an initial ESD event. By using a blocking device such as a diode, the power clamping circuit is maintained in a strong “on” state that fully discharges the initial ESD event and allows for a more rapid response to subsequent ESD events.

Scrambling Of Data Streams Having Arbitrary Data Path Widths

US Patent:
2004009, May 13, 2004
Filed:
Nov 7, 2002
Appl. No.:
10/289999
Inventors:
Frank Moore - Durham NC, US
Kevin Traynor - Cary NC, US
International Classification:
H04K001/04
US Classification:
380/037000
Abstract:
An arrangement is described for scrambling data streams having arbitrary data path widths. The arrangement includes logic configured to generate a maximal length pseudorandom sequence of digital signals. A first register is configured to store the pseudorandom sequence. Logic, coupled to the first register, is configured to combine a portion of the pseudorandom sequence with a corresponding portion of an input data stream to produce a scrambled data word. A second register is configured to store the scrambled data word. Circuitry is configured to circularly shift the pseudorandom sequence a number of bits forming the portion of the pseudorandom sequence used to produce the scrambled data word.

Method And System For Interrupt Mapping

US Patent:
2005002, Jan 27, 2005
Filed:
Jul 24, 2003
Appl. No.:
10/626756
Inventors:
Kevin Traynor - Cary NC, US
Jon Brabender - Cary NC, US
International Classification:
G06F013/24
US Classification:
710262000
Abstract:
A method and system are described for sharing a plurality of interrupt inputs associated with a processor among a plurality of interrupt sources. Each of the plurality of interrupt sources is mapped to each of the plurality of interrupt inputs. Interrupt requests from each of the plurality of interrupt sources to one or more of the plurality of interrupt inputs are selectively enabled, e.g., via control bits. The control bits are preferably dynamically modifiable according to user preferences.

Semiconductor Cell Blocks Having Non-Integer Multiple Of Cell Heights

US Patent:
2023010, Apr 6, 2023
Filed:
Oct 20, 2022
Appl. No.:
18/048186
Inventors:
- Suwon-si, KR
Joon Goo Hong - Austin TX, US
Kevin Traynor - Livingston TX, US
Tanya Abaya - Austin TX, US
Dharmendar Palle - Austin TX, US
Mark S. Rodder - Dallas TX, US
International Classification:
H01L 27/02
G06F 30/392
H01L 23/528
Abstract:
A semiconductor cell block includes a series of layers arranged in a stack. The layers include one or more first layers each having a first height and one or more second layers each having a second height. The second height is larger than the first height, and the second height is a non-integer multiple of the first height. The semiconductor cell block also includes a first semiconductor logic cell having a first cell height in one of the series of layers, and a second semiconductor logic cell having a second cell height in one of the series of layers. The second cell height is larger than the first cell height, and the second cell height is a non-integer value multiple of the first cell height.

Semiconductor Cell Blocks Having Non-Integer Multiple Of Cell Heights

US Patent:
2021026, Aug 26, 2021
Filed:
Apr 20, 2020
Appl. No.:
16/853535
Inventors:
- Suwon-si, KR
Joon Goo Hong - Austin TX, US
Kevin Traynor - Livingston TX, US
Tanya Abaya - Austin TX, US
Dharmendar Palle - Austin TX, US
Mark S. Rodder - Dallas TX, US
International Classification:
H01L 27/02
H01L 23/528
G06F 30/392
Abstract:
A semiconductor cell block includes a series of layers arranged in a stack. The layers include one or more first layers each having a first height and one or more second layers each having a second height. The second height is larger than the first height, and the second height is a non-integer multiple of the first height. The semiconductor cell block also includes a first semiconductor logic cell having a first cell height in one of the series of layers, and a second semiconductor logic cell having a second cell height in one of the series of layers. The second cell height is larger than the first cell height, and the second cell height is a non-integer value multiple of the first cell height.

Power Distribution Network Using Buried Power Rail

US Patent:
2020037, Nov 26, 2020
Filed:
Sep 5, 2019
Appl. No.:
16/561340
Inventors:
- Suwon-si, KR
Joon Goo Hong - Austin TX, US
Kevin Michael Traynor - Livingston TX, US
International Classification:
H01L 23/528
H01L 23/522
Abstract:
A tap cell configured to enable electrical connection from a buried power rail of an integrated circuit to a power distribution network includes. The tap cell includes a buried power rail layer including VDD and VSS power supply lines, insulating layers and metal layers alternately arranged on the buried power rail layer, a first power supply interconnect in metal layer M1 or higher electrically coupled to the VDD power supply line, and a second power supply interconnect in metal layer M1 or higher electrically connected to the VSS power supply line. The first power supply interconnect and the second power supply interconnect are configured to be electrically connected to the power distribution network, and the VDD and VSS power supply lines are configured to supply power from the power distribution network to the buried power rail of the integrated circuit. The tap cell is free of any active semiconductor devices.

Possible Relatives

David R Traynor  Dawn M Traynor  Dale E Traynor  Daniel P Traynor  Dennis M Traynor  Darla J Traynor  Diane M Traynor  Kevin T Johnson  Kevin Stamps  Kevin Stanberry 

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