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Kieu Loan Do, 562067 Colusa Way, San Jose, CA 95130

Known as:
Kieu L Do Kieu-Loan T Do Kieu Loan Tdo Loan T Do Kieu Loan Kieu Loan Dokieu Kieu Dam Loan Thido Kieu Kieuloan Do Kieu Thido
Related to:
Christine T Do 50

Kieu Do Phones & Addresses

2067 Colusa Way, San Jose, CA 95130   

807 2Nd St, San Jose, CA 95112   

Campbell, CA   

Morgan Hill, CA   

Las Vegas, NV   

Cupertino, CA   

Westminster, CA   

Santa Clara, CA   

Albuquerque, NM   

3315 Famille Ct, San Jose, CA 95135   

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Career records & work history

License Records

Kieu Do

Phone:
407-8162006
Licenses:
License #: 13302 - Expired
Category: Health Care
Issued Date: Aug 18, 2000
Effective Date: Dec 1, 2004
Type: Pharmacist Intern

Kieu Do resumes & CV records

Resumes

Kieu Do Photo 29

Accounting Associate

Location:
San Jose, CA
Industry:
Accounting
Work:

Accounting Associate
Education:
San Jose State University 2012 - 2017
Skills:
Customer Service
Kieu Do Photo 30

Kieu Do

Location:
United States

Publications & IP owners

Us Patents

Testing Soc With Portable Scenario Models And At Different Levels

US Patent:
2019039, Dec 26, 2019
Filed:
Aug 27, 2019
Appl. No.:
16/553083
Inventors:
- San Jose CA, US
Kairong Qian - San Jose CA, US
Kieu Do - San Jose CA, US
Joerg Grosse - Munich, DE
International Classification:
G01R 31/3177
G01R 31/3181
G06F 17/50
G06F 3/0484
G06F 11/36
G06F 11/22
G06F 11/263
G06T 11/20
G06F 9/48
G06F 11/25
Abstract:
A method for testing a system-on-a-chip (SoC) is described. The method includes parsing a file to determine functions to be performed components of the SoC. The method further includes receiving a desired output of the SoC and generating a test scenario model based on the desired output of the SoC. The test scenario model includes a plurality of module representations of the functions and includes one or more connections between two of the module representations. The desired output acts as a performance constraint for the test scenario model. The test scenario model further includes an input of the SoC that is generated based on the desired output, the module representations, and the one or more connections. The test scenario model includes a path from the input via the module representations and the connections to the desired output.

Scheduling Of Scenario Models For Execution Within Different Computer Threads And Scheduling Of Memory Regions For Use With The Scenario Models

US Patent:
2019031, Oct 17, 2019
Filed:
Jun 27, 2019
Appl. No.:
16/455642
Inventors:
- San Jose CA, US
Kairong Qian - San Jose CA, US
Kieu Do - San Jose CA, US
Joerg Grosse - Munich, DE
International Classification:
G01R 31/3177
G01R 31/3181
G06F 9/48
G06F 17/50
G06F 11/22
G06T 11/20
G06F 11/36
G06F 11/263
G06F 3/0484
G06F 11/25
Abstract:
A method for testing a system-on-a-chip (SoC) is described. The method includes parsing a file to determine functions to be performed by components of the SoC. The method further includes receiving a desired output of the SoC and generating a test scenario model based on the desired output of the SoC. The test scenario model includes a plurality of module representations of the functions and includes one or more connections between two of the module representations. The desired output acts as a performance constraint for the test scenario model. The test scenario model further includes an input of the SoC that is generated based on the desired output, the module representations, and the one or more connections. The test scenario model includes a path from the input via the module representations and the connections to the desired output.

Scheduling Of Scenario Models For Execution Within Different Computer Threads And Scheduling Of Memory Regions For Use With The Scenario Models

US Patent:
2018013, May 17, 2018
Filed:
Jan 11, 2018
Appl. No.:
15/868940
Inventors:
- San Jose CA, US
Kairong Qian - San Jose CA, US
Kieu Do - San Jose CA, US
Joerg Grosse - Munich, DE
International Classification:
G01R 31/3177
G06F 11/263
G06F 17/50
G01R 31/3181
G06F 11/25
G06F 9/48
Abstract:
A method for testing a system-on-a-chip (SoC) is described. The method includes parsing a file to determine functions to be performed by components of the SoC. The method further includes receiving a desired output of the SoC and generating a test scenario model based on the desired output of the SoC. The test scenario model includes a plurality of module representations of the functions and includes one or more connections between two of the module representations. The desired output acts as a performance constraint for the test scenario model. The test scenario model further includes an input of the SoC that is generated based on the desired output, the module representations, and the one or more connections. The test scenario model includes a path from the input via the module representations and the connections to the desired output.

Testing Soc With Portable Scenario Models And At Different Levels

US Patent:
2017027, Sep 28, 2017
Filed:
Jun 13, 2017
Appl. No.:
15/621995
Inventors:
- San Jose CA, US
Kairong Qian - San Jose CA, US
Kieu Do - San Jose CA, US
Joerg Grosse - Munich, DE
International Classification:
G01R 31/3177
G06T 11/20
G06F 3/0484
Abstract:
A method for testing a system-on-a-chip (SoC) is described. The method includes parsing a file to determine functions to be performed components of the SoC. The method further includes receiving a desired output of the SoC and generating a test scenario model based on the desired output of the SoC. The test scenario model includes a plurality of module representations of the functions and includes one or more connections between two of the module representations. The desired output acts as a performance constraint for the test scenario model. The test scenario model further includes an input of the SoC that is generated based on the desired output, the module representations, and the one or more connections. The test scenario model includes a path from the input via the module representations and the connections to the desired output.

Scheduling Of Scenario Models For Execution Within Different Computer Threads And Scheduling Of Memory Regions For Use With The Scenario Models

US Patent:
2017022, Aug 10, 2017
Filed:
Apr 26, 2017
Appl. No.:
15/497634
Inventors:
- San Jose CA, US
Kairong Qian - San Jose CA, US
Kieu Do - San Jose CA, US
Joerg Grosse - Munich, DE
International Classification:
G01R 31/3177
G06F 17/50
G01R 31/3181
G06F 11/263
G06F 9/48
G06F 11/25
Abstract:
A method for testing a system-on-a-chip (SoC) is described. The method includes parsing a file to determine functions to be performed components of the SoC. The method further includes receiving a desired output of the SoC and generating a test scenario model based on the desired output of the SoC. The test scenario model includes a plurality of module representations of the functions and includes one or more connections between two of the module representations. The desired output acts as a performance constraint for the test scenario model. The test scenario model further includes an input of the SoC that is generated based on the desired output, the module representations, and the one or more connections. The test scenario model includes a path from the input via the module representations and the connections to the desired output.

Display In A Graphical Format Of Test Results Generated Using Scenario Models

US Patent:
2016026, Sep 15, 2016
Filed:
May 19, 2016
Appl. No.:
15/159576
Inventors:
- San Jose CA, US
Kairong Qian - San Jose CA, US
Kieu Do - San Jose CA, US
Joerg Grosse - Munich, DE
International Classification:
G01R 31/3177
G06T 11/20
Abstract:
A method for testing a system-on-a-chip (SoC) is described. The method includes parsing a file to determine functions to be performed components of the SoC. The method further includes receiving a desired output of the SoC and generating a test scenario model based on the desired output of the SoC. The test scenario model includes a plurality of module representations of the functions and includes one or more connections between two of the module representations. The desired output acts as a performance constraint for the test scenario model. The test scenario model further includes an input of the SoC that is generated based on the desired output, the module representations, and the one or more connections. The test scenario model includes a path from the input via the module representations and the connections to the desired output.

Scheduling Of Scenario Models For Execution Within Different Computer Threads And Scheduling Of Memory Regions For Use With The Scenario Models

US Patent:
2016020, Jul 21, 2016
Filed:
Mar 25, 2016
Appl. No.:
15/081740
Inventors:
- San Jose CA, US
Kairong Qian - San Jose CA, US
Kieu Do - San Jose CA, US
Joerg Grosse - Munich, DE
International Classification:
G01R 31/3177
G06F 17/50
Abstract:
A method for testing a system-on-a-chip (SoC) is described. The method includes parsing a file to determine functions to be performed components of the SoC. The method further includes receiving a desired output of the SoC and generating a test scenario model based on the desired output of the SoC. The test scenario model includes a plurality of module representations of the functions and includes one or more connections between two of the module representations. The desired output acts as a performance constraint for the test scenario model. The test scenario model further includes an input of the SoC that is generated based on the desired output, the module representations, and the one or more connections. The test scenario model includes a path from the input via the module representations and the connections to the desired output.

Testing Soc With Portable Scenario Models And At Different Levels

US Patent:
2016019, Jul 7, 2016
Filed:
Feb 26, 2016
Appl. No.:
15/055404
Inventors:
- San Jose CA, US
Kairong Qian - San Jose CA, US
Kieu Do - San Jose CA, US
Joerg Grosse - Munich, DE
International Classification:
G06F 11/263
G06F 11/22
Abstract:
A method for testing a system-on-a-chip (SoC) is described. The method includes parsing a file to determine functions to be performed components of the SoC. The method further includes receiving a desired output of the SoC and generating a test scenario model based on the desired output of the SoC. The test scenario model includes a plurality of module representations of the functions and includes one or more connections between two of the module representations. The desired output acts as a performance constraint for the test scenario model. The test scenario model further includes an input of the SoC that is generated based on the desired output, the module representations, and the one or more connections. The test scenario model includes a path from the input via the module representations and the connections to the desired output.

Possible Relatives

David Do  De D Do  Deanne Do  Damon D Do  Dang T Do  Danh T Do  Dao T Do  Kieu T Ti  Kieu T Nguyen  Kieu T Pham 

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