Kuen C Chow, 804899 Coyote Wells Cir, Westlake Village, CA 91362
Kuen Chow Phones & Addresses
1684 Calle Yucca, Thousand Oaks, CA 91360 408-9276508
Westlake Village, CA
San Jose, CA
Fremont, CA
6559 Stonehill Dr, San Jose, CA 95120
Work
Position:
Professional/Technical
Education
Degree:
Associate degree or higher
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Mentions for Kuen C Chow
Publications & IP owners
Us Patents
Temperature Gradient Zone Melting Apparatus
US Patent:
4523067, Jun 11, 1985
Filed:
Apr 9, 1982
Appl. No.:
6/366901
Inventors:
Roger H. Brown - Burbank CA
Kuen Chow - Thousand Oaks CA
Norman W. Goodwin - Encino CA
Jan Grinberg - Los Angeles CA
Kuen Chow - Thousand Oaks CA
Norman W. Goodwin - Encino CA
Jan Grinberg - Los Angeles CA
Assignee:
Hughes Aircraft Company - El Segundo CA
International Classification:
H05B 610
US Classification:
219 1049R
Abstract:
An apparatus is provided for fabricating a semiconductor device by thermal gradient zone melting, whereby metal-rich droplets such as aluminum migrate through a semiconductor wafer such as silicon to create conductive paths. One surface of the wafer is placed directly on a heating surface to establish a high and uniform thermal gradient through the wafer. Heat in the wafer is removed from the other wafer surface. The apparatus for fabricating semiconductor devices utilizing temperature gradient zone melting comprises a base, heating means and heat sink means. Heating means comprises a platform having a generally planar heating surface adapted to receive the entire area of the one surface of at least one wafer. The heat sink means is spaced away from the other wafer surface to form a space therebetween, the space being adapted to receive a high heat conductive gas. The heat sink means and the gas cooperatively remove the heat in the wafer to enhance the establishment of the thermal gradient.
Semiconductor Light Valve Having Improved Counterelectrode Structure
US Patent:
4239347, Dec 16, 1980
Filed:
May 29, 1979
Appl. No.:
6/043077
Inventors:
Paul O. Braatz - Canoga Park CA
Kuen Chow - Thousand Oaks CA
Jan Grinberg - Los Angeles CA
Kuen Chow - Thousand Oaks CA
Jan Grinberg - Los Angeles CA
Assignee:
Hughes Aircraft Company - Culver City CA
International Classification:
G02F 1135
US Classification:
350336
Abstract:
A liquid crystal light valve having an improved counterelectrode structure. The light valve includes a layer of liquid crystal material which lies intermediate a photosensitive substrate of intrinsic semiconductive material and the counterelectrode. The upper surface of the substrate is characterized by a highly doped peripheral channel stop. The counterelectrode comprises electrically insulated inner and outer regions, the inner region substantially overlying only the intrinsic material interior said highly doped peripheral channel stop so that an electrical bias may be selectively applied, greatly enhancing the dark current breakdown voltage of the device.
Pre-Multiplexed Schottky Barrier Focal Plane
US Patent:
4467340, Aug 21, 1984
Filed:
Nov 16, 1981
Appl. No.:
6/321360
Inventors:
Jonathan P. Rode - Thousand Oaks CA
Kuen Chow - Thousand Oaks CA
Kuen Chow - Thousand Oaks CA
Assignee:
Rockwell International Corporation - El Segundo CA
International Classification:
H01L 2978
H01L 2714
H01L 3100
H01L 2956
H01L 2714
H01L 3100
H01L 2956
US Classification:
357 24
Abstract:
Disclosed is a hybrid Schottky barrier focal plane, which includes a transparent semiconducting detector substrate of a first conductivity, with an array of detector groups disposed on the detector substrate, each group including a plurality of Schottky barrier detectors. An output contact is provided on the detector substrate for each of the detector groups. A field effect transistor for each detector includes a source region of a second conductivity type in the detector substrate and connected to the detector, a drain region of the second conductivity type in the detector substrate over the source and drain regions for controlling the connection between the source region and the drain region. An array of output contacts are disposed on a semiconducting multiplexer substrate, which also includes a charge coupled circuit for converting parallel signals from the input contacts to a serial output signal. An array of coupling elements is provided to connect each of the output contacts on the detector substrate to one of the input contacts on the multiplexer substrate.
Temperature Gradient Zone Melting Process Employing A Buffer Layer
US Patent:
4398974, Aug 16, 1983
Filed:
Apr 9, 1982
Appl. No.:
6/366900
Inventors:
Kuen Chow - Thousand Oaks CA
Jan Grinberg - Los Angeles CA
Jan Grinberg - Los Angeles CA
Assignee:
Hughes Aircraft Company - El Sequndo CA
International Classification:
H01L 21228
US Classification:
148171
Abstract:
A process is provided for fabricating a semiconductor device by thermal gradient zone melting, whereby metal-rich droplets such as aluminum migrate through a semiconductor wafer such as silicon to create conductive paths. One surface of the wafer in provided with a buffer layer thereon, which is placed directly on a heating surface. The buffer layer terminates the migration of the droplets to prevent alloying of the droplets with the heating surface.
Three-Dimensionally Structured Microelectronic Device
US Patent:
4275410, Jun 23, 1981
Filed:
Nov 29, 1978
Appl. No.:
5/964547
Inventors:
Jan Grinberg - Los Angeles CA
Alexander D. Jacobson - Los Angeles CA
Kuen Chow - Thousand Oaks CA
Alexander D. Jacobson - Los Angeles CA
Kuen Chow - Thousand Oaks CA
Assignee:
Hughes Aircraft Company - Culver City CA
International Classification:
H01L 2348
US Classification:
357 68
Abstract:
A large scale parallel architecture in which many parallel channels numbering 10. sup. 2 or more operate simultaneously to create a natural and efficient organization for processing two-dimensional arrays of data. The architecture comprises a plurality of stack integrated circuit wafers having top and bottom surfaces, electric signal paths extending through each of the wafers between the surfaces, and micro-interconnects (smaller than 50 mil) on the surfaces of adjacent wafers interconnecting the respective eletric signal paths with a topographical one-to-one correspondence.
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