Kulbhushan Kalra, 502084 Purcell Pl, San Jose, CA 95131
Kulbhushan Kalra Phones & Addresses
2084 Purcell Pl, San Jose, CA 95131
1430 Cedarmeadow Ct, San Jose, CA 95131
1235 Wildwood Ave, Sunnyvale, CA 94089
3655 Pruneridge Ave, Santa Clara, CA 95051
Sanger, CA
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Us Patents
Protection Scheme For Embedded Code
US Patent:
2017004, Feb 16, 2017
Filed:
Oct 31, 2016
Appl. No.:
15/339859
Inventors:
- Mountain View CA, US
Carlos Basto - Mountain View CA, US
Kulbhushan Kalra - Mountain View CA, US
Carlos Basto - Mountain View CA, US
Kulbhushan Kalra - Mountain View CA, US
International Classification:
G06F 12/14
G06F 21/62
G06F 9/38
G06F 21/78
G06F 21/79
G06F 21/52
G06F 21/71
G06F 21/62
G06F 9/38
G06F 21/78
G06F 21/79
G06F 21/52
G06F 21/71
Abstract:
A code protection scheme for controlling access to a memory region in an integrated circuit includes a processor with an instruction pipeline that includes multiple processing stages. A first processing stage receives one or more instructions. A second processing stage receives address information identifying a protected memory region of the memory from the first processing stage and protection information for an identified protected memory region. The protection information indicates a protection state assigned to each protected memory region. Based on the instruction type of the received instruction and the protection information associated with a particular protected memory region, the second processing stage determines whether to enable or disable access to the particular protected memory region by the processor or other external host.
Protection Scheme For Embedded Code
US Patent:
2015022, Aug 6, 2015
Filed:
Aug 14, 2013
Appl. No.:
14/421799
Inventors:
- Mountain View CA, US
Carlos Basto - Mountain View CA, US
Kulbhushan Kalra - Mountain View CA, US
Carlos Basto - Mountain View CA, US
Kulbhushan Kalra - Mountain View CA, US
Assignee:
Synopsys, Inc. - Mountain View CA
International Classification:
G06F 12/14
G06F 9/38
G06F 21/62
G06F 9/38
G06F 21/62
Abstract:
A code protection scheme for controlling access to a memory region in an integrated circuit includes a processor with an instruction pipeline that includes multiple processing stages. A first processing stage receives one or more instructions. A second processing stage receives address information identifying a protected memory region of the memory from the first processing stage and protection information for an identified protected memory region. The protection information indicates a protection state assigned to each protected memory region. Based on the instruction type of the received instruction and the protection information associated with a particular protected memory region, the second processing stage determines whether to enable or disable access to the particular protected memory region by the processor or other external host.
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