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Kuljit Singh Bains, 58Dupont, WA

Known as:
Kuljit S Bains Kuljit S Singha Kuljit Bains Singh Bains Kuljit David Manbeck
Related to:
Hardeep Singh 57

Kuljit Bains Phones & Addresses

Dupont, WA   

1156 Alki Ave SW, Seattle, WA 98116   

3053 Alki Ave SW APT B, Seattle, WA 98116   

Kihei, HI   

Madison, WI   

9146 52Nd Ave, Lacey, WA 98516    360-4599667   

Olympia, WA   

Folsom, CA   

1156 Alki Ave SW, Seattle, WA 98116    206-8950495   

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Kuljit Bains resumes & CV records

Resumes

Kuljit Bains Photo 23

Senior Principal Engineer

Location:
1156 Alki Ave southwest, Seattle, WA 98116
Industry:
Computer Hardware
Work:
Intel Corporation
Senior Principal Engineer Qualcomm Aug 2016 - Jun 2018
Principal Engineer Memory Technologies Intel Corporation Sep 1990 - Jul 2016
Principal Engineer Memory Technologies
Education:
California State University - Sacramento 1988 - 1990
Master of Science, Masters, Electrical Engineering Motilal Nehru National Institute of Technology 1984 - 1988
Bachelors, Bachelor of Science, Electronics
Skills:
Semiconductors, Ic, Ddr3, Dram, Soc, Mixed Signal, Asic, Processors, Cmos, Hardware Architecture, Intel, Embedded Systems, Verilog, Dynamic Random Access Memory, Microprocessors, Mobile Devices, Semiconductor Industry, Circuit Design, Fpga, Analog, Integrated Circuits, Debugging, System on A Chip, Eda, Rtl Design, Signal Integrity, Analog Circuit Design, Application Specific Integrated Circuits, Architectures
Kuljit Bains Photo 24

Kuljit Bains

Kuljit Bains Photo 25

Kuljit Bains

Skills:
Microsoft Office, Microsoft Word
Kuljit Bains Photo 26

Kuljit Bains

Publications & IP owners

Us Patents

Method And System For Symmetric Memory Population

US Patent:
6366983, Apr 2, 2002
Filed:
Sep 14, 1999
Appl. No.:
09/396802
Inventors:
Kuljit S. Bains - Seattle WA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 1316
US Classification:
711115, 711 5, 711170
Abstract:
A processing system and method allow for the population of a memory system while maintaining communication symmetry. The processing system has multiple communication channels which have the same propagation path lengths. The memory system can be expanded by adding additional memory device pairs. The system and method allow for the configuration of the computer memory in a symmetric manner with respect to either communication channels, or physical memory socket locations. In addition, a method uses a computer BIOS to determine locations of new memory devices and adjust the communication configuration. The configuration is defined by address channel identifiers, such as an identification bit.

Method For Opening Pages Of Memory With A Single Command

US Patent:
6785190, Aug 31, 2004
Filed:
May 20, 2003
Appl. No.:
10/442335
Inventors:
Kuljit S. Bains - Olympia WA
John Halbert - Beaverton OR
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G11C 800
US Classification:
365235, 36523003
Abstract:
An efficient invention for opening two pages of memory for a DRAM are discussed.

Techniques To Map Cache Data To Memory Arrays

US Patent:
6954822, Oct 11, 2005
Filed:
Aug 2, 2002
Appl. No.:
10/211680
Inventors:
Kuljit S. Bains - Olympia WA, US
Herbert Hum - Portland OR, US
John Halbert - Beaverton OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F012/00
US Classification:
711 5, 711 3, 711128, 36523002, 36523003, 365239
Abstract:
Methods and apparatuses for mapping cache contents to memory arrays. In one embodiment, an apparatus includes a processor portion and a cache controller that maps the cache ways to memory banks. In one embodiment, each bank includes data from one cache way. In another embodiment, each bank includes data from each way. In another embodiment, memory array banks contain data corresponding to sequential cache lines.

Method And Apparatus For Multiple Row Caches Per Bank

US Patent:
6990036, Jan 24, 2006
Filed:
Dec 30, 2003
Appl. No.:
10/749690
Inventors:
John B. Halbert - Beaverton OR, US
Robert M. Ellis - Hillsboro OR, US
Kuljit S. Bains - Olympia WA, US
Chris B. Freeman - Portland OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G11C 7/00
US Classification:
36523003, 365198
Abstract:
Provision and use of sets of isolators to enable the caching of the contents of at least one row of memory cells within a subarray of a bank of a memory device by a row of sense amplifiers associated with the subarray to enable faster access to write the data directed to at least one row through a write operation causing the data to written to the row of sense amplifiers versus from the row of memory cells, directly, and to store an indication that the data cached by the row of sense amplifiers is dirty.

Method And Apparatus For Providing Debug Functionality In A Buffered Memory Channel

US Patent:
6996749, Feb 7, 2006
Filed:
Nov 13, 2003
Appl. No.:
10/713564
Inventors:
Kuljit S. Bains - Olympia WA, US
Robert M. Ellis - Hillsboro OR, US
Chris B. Freeman - Portland OR, US
John B. Halbert - Beaverton OR, US
David Zimmerman - El Dorado Hills CA, US
Assignee:
Intel Coporation - Santa Clara CA
International Classification:
G06F 11/00
US Classification:
714 42, 714742
Abstract:
Some embodiments of the invention enable debugging functionality for memory devices residing on a memory module that are buffered from the memory bus by a buffer chip. Some embodiments map connector signals from a tester coupled to the high speed interface between the buffer chip and the memory bus to an interface between the buffer chip and the memory devices. During test mode, some embodiments bypass the normal operational circuitry of the buffer chip and provide a direct connection to the memory devices. Other embodiments use the existing architecture of the buffer chip to convert high speed pins into low speed pins and map them to pins that are connected to the memory devices. Other embodiments are described in the claims.

Method And Apparatus For Multiple Row Caches Per Bank

US Patent:
7050351, May 23, 2006
Filed:
Dec 30, 2003
Appl. No.:
10/750038
Inventors:
John B. Halbert - Beaverton OR, US
Robert M. Ellis - Hillsboro OR, US
Kuljit S. Bains - Olympia WA, US
Chris B. Freeman - Portland OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G11C 8/00
US Classification:
36523003, 36523008
Abstract:
Provision and use of sets of isolators to enable the caching of the contents of at least one row of memory cells within a subarray of a bank of a memory device by a row of sense amplifiers associated with the subarray to enable faster access to read the contents of that at least one row through a read operation causing the data to read from the row of sense amplifiers versus from the row of memory cells, directly.

High Speed Dram Cache Architecture

US Patent:
7054999, May 30, 2006
Filed:
Aug 2, 2002
Appl. No.:
10/210908
Inventors:
Kuljit S. Bains - Olympia WA, US
Herbert Hum - Portland OR, US
John Halbert - Beaverton OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 12/08
US Classification:
711128, 711105, 711145, 711167, 36523002, 36523003
Abstract:
A high speed DRAM cache architecture. One disclosed embodiment includes a multiplexed bus interface to interface with a multiplexed bus. A cache control circuit drives a row address portion of an address on the multiplexed bus interface and a command to open a memory page containing data for a plurality of ways. The cache control circuit subsequently drives a column address including at least a way indicator to the multiplexed bus interface.

Fine Granularity Dram Refresh

US Patent:
7221609, May 22, 2007
Filed:
Dec 28, 2005
Appl. No.:
11/321367
Inventors:
Kuljit S. Bains - Olympia WA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G11C 7/00
US Classification:
365222, 365236, 365239
Abstract:
A method, device, and system are included. In one embodiment, the method included issuing a single row refresh command for a first row in a memory starting at a target address, incrementing a row counter, continuing issuing a single row refresh command for each subsequent row in the memory and incrementing the row counter until the number of row counter increments is equal to the number of rows of the memory refreshed as a result of a refresh (REF) command.

Possible Relatives

David T Bains  Davinder K Bains  Deborah S Bains  Devinder K Bains  Gurdev Bains  Gurjeet S Bains  Harcharan J Bains  Kuljit K Grewal  Kuljit Kaur  Kuljit Rathor 

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