Kun Xu, 5110300 Echoridge Dr, Austin, TX 78750

7894440, Feb 22, 2011

Mar 13, 2009

12/404140

Kun Xu - Austin TX, US
David Kramer - Cedar Park TX, US

Freescale Semiconductor, Inc. - Austin TX

H04L 12/56

370392, 709223

Techniques have been developed to facilitate concurrent evaluation of hash rule entries in ways that allow an implementation to maintain a deterministic resultant hash irrespective of variations in the allocation of particular rules to particular storage banks or evaluation logic, such as may occur with rule set revisions. Similarly, uniform deterministic hash results can be assured even across a range of implementations that support greater or lesser levels of concurrent rule evaluations.

8136001, Mar 13, 2012

Jun 5, 2009

12/479535

Kun Xu - Austin TX, US
Jen-Tien Yen - Austin TX, US
Robert Serphillips - Austin TX, US

Freescale Semiconductor, Inc. - Austin TX

G01R 31/28

714724, 714726

Techniques have been developed to introduce processor core functional pattern tests into a memory space addressable by at least one processor core of an integrated circuit. In general, such functional pattern tests can include both instruction sequences and data patterns and, in some embodiments in accordance with the present invention, are introduced (at least in part) into on-chip cache memory using facilities of an on-chip loader. Instruction opcodes used in functional test sequences may be efficiently introduced into a plurality of target locations in memory (e. g. , at locations corresponding to multiple interrupt handlers or at locations from which a multiplicity of cores execute their functional tests) using facilities of the on-chip loader. In some embodiments, instruction selections together with a base address, extent and stride indications may be used to direct operation of the on-chip loader. Likewise, data patterns used in the functional test sequences may be specified as a data pattern selection together with base address, extent and optional stride indications and introduced into a plurality of target memory locations using facilities of the on-chip loader.

8291417, Oct 16, 2012

Sep 8, 2006

11/530051

Kun Xu - Austin TX, US
Jen-Tien Yen - Austin TX, US

Freescale Semiconductor, Inc. - Austin TX

G06F 9/46
G06F 11/00
G06F 3/00

718100, 710 56, 714 30, 714 45

A method includes storing a first transaction entry to a first software configurable storage location, storing a second transaction entry to a second software configurable storage location, determining that a first transaction indicated by the first transaction entry has occurred, determining that a second transaction indicated by the second transaction entry has occurred subsequent to the first transaction, and, in response to determining that the first transaction occurred and the second transaction occurred, storing at least one transaction attribute captured during at least one clock cycle subsequent to the second transaction. The first and second software configurable storage locations may be located in a trace buffer, where the at least one transaction attribute is stored to the trace buffer and overwrites the first and second transaction attributes. Each transaction entry may include a dead cycle field, a consecutive transaction requirement field, and a last entry field.

8447897, May 21, 2013

Jun 24, 2011

13/168331

Kun Xu - Austin TX, US
Tommi M. Jokinen - Austin TX, US
David B. Kramer - Cedar Park TX, US

Freescale Semiconductor, Inc. - Austin TX

G06F 3/00
G06F 5/00

710 24, 710308

A method for controlling bandwidth in a direct memory access (DMA) unit of a computer processing system, the method comprising: assigning a DMA job to a selected DMA engine; starting a source timer; and issuing a request to read a next section of data for the DMA job. If a sufficient amount of the data was not obtained, allowing the DMA engine to wait until the source timer reaches a specified value before continuing to read additional data for the DMA job.

8560796, Oct 15, 2013

Mar 29, 2010

12/748617

Kun Xu - Austin TX, US
David B Kramer - Cedar Park TX, US

Freescale Semiconductor, Inc. - Austin TX

G06F 13/18

711167

A data processing system employs an improved arbitration process in selecting pending memory access requests received from the one or more processor cores for servicing by the memory. The arbitration process uses memory timing and state information pertaining both to memory access requests already submitted to the memory for servicing and to the pending memory access requests which have not yet been selected for servicing by the memory. The memory timing and state information may be predicted memory timing and state information; that is, the component of the data processing system that implements the improved scheduling algorithm may not be able to determine the exact point in time at which a memory controller initiates a memory access for a corresponding memory access request and thus the component maintains information that estimates or otherwise predicts the particular state of the memory at any given time.

8572322, Oct 29, 2013

Mar 29, 2010

12/748600

Kun Xu - Austin TX, US
David B Kramer - Cedar Park TX, US
James A. Welker - Leander TX, US

Freescale Semiconductor, Inc. - Austin TX

G06F 13/12

711122

A data processing system employs a scheduler to schedule pending memory access requests and a memory controller to service scheduled pending memory access requests. The memory access requests are asynchronously scheduled with respect to the clocking of the memory. The scheduler is operated using a clock signal with a frequency different from the frequency of the clock signal used to operate the memory controller. The clock signal used to clock the scheduler can have a lower frequency than the clock used by a memory controller. As a result, the scheduler is able to consider a greater number of pending memory access requests when selecting the next pending memory access request to be submitted to the memory for servicing and thus the resulting sequence of selected memory access requests is more likely to be optimized for memory access throughput.

8615614, Dec 24, 2013

Nov 30, 2011

13/307271

Kun Xu - Austin TX, US
Tommi M. Jokinen - Austin TX, US
David B. Kramer - Cedar Park TX, US

Freescale Semiconductor, Inc. - Austin TX

G06F 13/28
G06F 12/00

710 26, 711117

A method includes generating, by a first software process of the data processing system, a source partition descriptor for a DMA job which requires access to a first partition of a memory which is assigned to a second software process of the data processing system and not assigned to the first software process. The source partition descriptor comprises a partition identifier which identifies the first partition of the memory. The DMA unit receives the source partition descriptor and generates a destination partition descriptor for the DMA job. Generating the destination partition descriptor includes translating, by the DMA unit, the partition identifier to a buffer pool identifier which identifies a physical address within the first partition of the memory which is assigned to the second software process; and storing, by the DMA unit, the buffer pool identifier in the destination partition descriptor.

8638800, Jan 28, 2014

Apr 3, 2009

12/418259

David Kramer - Cedar Park TX, US
Kun Xu - Austin TX, US

Freescale Semiconductor, Inc. - Austin TX

H04L 12/28

37039532, 710316

Techniques have been developed to facilitate evaluation of match and hash rule entries in ways that allow an implementation to decouple (i) the order in which match rules are applied to a first subset of packet header fields from (ii) the ordering of a second subset of packet header fields over which a non-commutative hash is computed. In short, the set and ordering of fields evaluated in accordance with a precedence order of rules need not correspond to the set or ordering of fields over which a hash is computed in a communications controller.