Kuo Kang Chang, 755561 Monticello Ave, Buena Park, CA 90621

6992370, Jan 31, 2006

Sep 4, 2003

10/655179

George J. Kluth - Campbell CA, US
Robert B. Clark-Phelps - San Jose CA, US
Joong S. Jeon - Cupertino CA, US
Huicai Zhong - Wappinger Falls NY, US
Arvind Halliyal - Cupertino CA, US
Mark T. Ramsbey - Sunnyvale CA, US
Kuo T. Chang - Saratoga CA, US
Wenmei Li - Sunnyvale CA, US

Advanced Micro Devices, Inc. - Sunnyvale CA

H01L 23/58
H01L 21/302

257640, 257649, 257760, 438257, 438724, 438774

According to one embodiment, a memory cell structure comprises a semiconductor substrate, a first silicon oxide layer situated over the semiconductor substrate, a charge storing layer situated over the first silicon oxide layer, a second silicon oxide layer situated over the charge storing layer, and a gate layer situated over the second silicon oxide layer. In the exemplary embodiment, the charge storing layer comprises silicon nitride having reduced hydrogen content, e. g. , in the range of about 0 to 0. 5 atomic percent. As a result, the reduced hydrogen content reduces the charge loss in the charge storing layer. The reduced charge loss in the charge storing layer has the benefit of reducing threshold voltage shifts, programming data loss, and programming capability loss in the memory device, thereby improving memory device performance.

8647969, Feb 11, 2014

Jan 31, 2012

13/362899

Rinji Sugino - San Jose CA, US
Yider Wu - Taipei County, TW
Minh Van Ngo - Fremont CA, US
Jeffrey Sinclair Glick - Cupertino CA, US
Kuo Tung Chang - Saratoga CA, US

Spansion LLC - Sunnyvale CA

H01L 21/20

438488, 257E21002

A method of manufacturing a memory device includes forming a first dielectric layer over a substrate, forming a charge storage element over the first dielectric layer and forming an inter-gate dielectric over the charge storage element. The method also includes depositing a silicon control gate layer over the inter-gate dielectric using a reactant that contains chlorine.

8208296, Jun 26, 2012

Feb 16, 2010

12/706710

Timothy Thurgate - Sunnyvale CA, US
Shenqing Fang - Fremont CA, US
Kuo Tung Chang - Saratoga CA, US
Youseok Suh - Cupertino CA, US

Spansion LLC - Sunnyvale CA

G11C 11/34

36518501, 36518524

A method and apparatus for storing information is provided. A core region of memory includes a semiconductor layer, at least one shallow trench, an insulator, and a charge-trapping layer. The semiconductor layer includes at least one source/drain region, and the insulator disposed above the source/drain region. The charge trapping layer is within the insulator, and the charge trapping layer is above the entire width of the source/drain region, and extends at least one angstrom beyond the width of the source/drain region, so that a portion the charge trapping layer extends into at least one shallow trench.

2009026, Oct 22, 2009

Apr 17, 2008

12/105208

Youseok SUH - Cupertino CA, US
Shenqing FANG - Fremont CA, US
Kuo Tung CHANG - Saratoga CA, US
Rinji SUGINO - San Jose CA, US
Yi MA - Santa Clara CA, US
Eunha KIM - Menlo Park CA, US

H01L 29/792
H01L 21/336

257325, 438287, 257E29309, 257E21423

A flash memory cell includes a charge storage element that includes at least a first layer and a second layer. One of the layers includes silicon-rich silicon nitride and the other layer includes silicon nitride. More specifically, the ratio of silicon-to-nitrogen in the first layer is greater than the ratio of silicon-to-nitrogen in the second layer.

2010021, Aug 26, 2010

Feb 23, 2009

12/390550

Gulzar A. Kathawala - Santa Clara CA, US
Zhizheng Liu - San Jose CA, US
Kuo Tung Chang - Saratoga CA, US
Lei Xue - Milpitas CA, US

SPANSION LLC - Sunnyvale CA

H01L 29/792
H01L 21/336
H01L 21/425

257324, 438261, 438514, 257E29309, 257E21409, 257E21473

Semiconductor devices having reduced parasitic current and methods of malting the semiconductor devices are provided. Further provided are memory devices having reduced adjacent wordline disturb. The memory devices contain wordlines formed over a semiconductor substrate, wherein at least one wordline space is formed between the wordlines. Adjacent wordline disturb is reduced by implanting one or more of indium, boron, and a combination of boron and indium in the surface of the at least one wordline space.

2021029, Sep 23, 2021

May 18, 2021

17/323819

- San Jose CA, US
James Pak - Sunnyvale CA, US
Unsoon KIM - San Jose CA, US
Inkuk Kang - San Jose CA, US
Kuo Tung Chang - Saratoga CA, US

Cypress Semiconductor Corporation - San Jose CA

H01L 27/11573
H01L 21/28
H01L 27/1157
H01L 29/66
H01L 29/792
H01L 21/265
H01L 21/285
H01L 27/11521
H01L 27/11546
H01L 27/11568
H01L 29/423
H01L 29/45
H01L 29/49
H01L 29/78

A semiconductor device and method of fabricating the same are disclosed. The method includes depositing a polysilicon gate layer over a gate dielectric formed over a surface of a substrate in a peripheral region, forming a dielectric layer over the polysilicon gate layer and depositing a height-enhancing (HE) film over the dielectric layer. The HE film, the dielectric layer, the polysilicon gate layer and the gate dielectric are then patterned for a high-voltage Field Effect Transistor (HVFET) gate to be formed in the peripheral region. A high energy implant is performed to form at least one lightly doped region in a source or drain region in the substrate adjacent to the HVFET gate. The HE film is then removed, and a low voltage (LV) logic FET formed on the substrate in the peripheral region. In one embodiment, the LV logic FET is a high-k metal-gate logic FET.

2021013, May 6, 2021

Nov 20, 2020

16/953643

- San Jose CA, US
James Pak - Sunnyvale CA, US
Unsoon Kim - San Jose CA, US
Inkuk Kang - San Jose CA, US
Kuo Tung Chang - Saratoga CA, US

Cypress Semiconductor Corporation - San Jose CA

H01L 27/1157
H01L 27/11573
H01L 29/423

Systems and methods of forming such include method, forming a memory gate (MG) stack in a first region, forming a sacrificial polysilicon gate on a high-k dielectric in a second region, wherein the first and second regions are disposed in a single substrate. Then a select gate (SG) may be formed adjacent to the MG stack in the first region of the semiconductor substrate. The sacrificial polysilicon gate may be replaced with a metal gate to form a logic field effect transistor (FET) in the second region. The surfaces of the substrate in the first region and the second region are substantially co-planar.

2021009, Mar 25, 2021

Sep 30, 2020

17/039603

- San Jose CA, US
Chun Chen - San Jose CA, US
Unsoon KIM - San Jose CA, US
Mark T. Ramsbey - Sunnyvale CA, US
Kuo Tung Chang - Saratoga CA, US
Sameer S. HADDAD - San Jose CA, US
James Pak - Sunnyvale CA, US

Cypress Semiconductor Corporation - San Jose CA

H01L 29/423
H01L 29/51
H01L 29/792
H01L 29/49
H01L 29/788
H01L 29/66
H01L 21/02
H01L 21/28
H01L 27/11568
H01L 27/11573
H01L 49/02

A semiconductor device and method of making the same are disclosed. The semiconductor device includes a memory gate on a charge storage structure formed on a substrate, a select gate on a gate dielectric on the substrate proximal to the memory gate, and a dielectric structure between the memory gate and the select gate, and adjacent to sidewalls of the memory gate and the select gate, wherein the memory gate and the select gate are separated by a thickness of the dielectric structure. Generally, the dielectric structure comprises multiple dielectric layers including a first dielectric layer adjacent the sidewall of the memory gate, and a nitride dielectric layer adjacent to the first dielectric layer and between the memory gate and the select gate. Other embodiments are also disclosed.