Lawrence R Wagner, 32Carmel, IN

4862346, Aug 29, 1989

Jul 2, 1985

6/751304

Lawrence F. Wagner - Berkeley CA
Korbin S. Van Dyke - Fremont CA
Wayne P. Burleson - Palo Alto CA
Robert D. Hemming - San Jose CA
John P. Guadagna - Morgan Hill CA

VLSI Technology, Inc. - San Jose CA

G06F 932

364200

A digital processor has four components: a controller, a data converter, a data register, and a logarithmic calculator. The processor has an address bus and a data bus for communication therewith. The address bus is connected to the controller. The data bus is connected to the controller and to the data register. Program instructions from the data bus are supplied to the controller and data on the data bus are supplied to the data register. Program instructions supplied to the controller are decoded and internal program instructions are generated by the controller. The controller communicates with the data converter, data register, and the logarithmic calculator via an internal bus through the internal program instructions. Integer data from the data bus are stored in the data register. The data converter receives the integer data, converts it into logarithmic data, and stores it in the data register.

4857882, Aug 15, 1989

Sep 14, 1988

7/245930

Lawrence F. Wagner - Berkeley CA
Wayne P. Burleson - Palo Alto CA
John P. Guadagna - Morgan Hill CA

VLSI Technology, Inc. - San Jose CA

G06F 702

3401462

A comparator array logic (CAL) circuit has a plurality of interconnected comparators arranged in an array. Each of the comparators stores a digital value. The CAL circuit stores all of the digital values in a monotonically increasing or decreasing order. Each of the comparators receives the input data signal and compares the input data signal to the digital value stored in the comparator. A comparison signal is generated in response to the comparison. The comparison signal from each comparator is received by an end cell which also receives the comparison signal from the immediately adjacent comparator. The end cell generates an output signal. An end cell is associated with each comparator. The plurality of output signals from the end cells represent the location of the comparator which borders the value of the input data signal.

4852038, Jul 25, 1989

Jul 2, 1985

6/751302

Lawrence F. Wagner - Berkeley CA
Wayne P. Burleson - Palo Alto CA
Korbin S. Van Dyke - Fremont CA

VLSI Techology, Inc. - San Jose CA

G06F 700
G06F 1500

3647485

A calculating apparatus receives four operands ("a, b, c and d") simultaneously. A first multiplier/divider performs the calculation of a*b or a. div. b and provides an output u. A second multiplier/divider performs the calculation of c*d or c. div. d and provides an output v. An adder/subtractor receives u and v and performed the calculation of u+v and u-v. A controller controls the operation of the first and second multiplier/divider to select the operation of multiplication or division.

4626825, Dec 2, 1986

Jul 2, 1985

6/751305

Wayne P. Burleson - Palo Alto CA
Lawrence F. Wagner - Berkeley CA
Korbin S. Van Dyke - Fremont CA

VLSI Technology, Inc. - San Jose CA

H03M 750

340347DD

A logarithmic converting apparatus for converting a digital binary integer into logarithmic representation and for converting logarithmic representation into digital binary integer is disclosed. The apparatus determines the bit position of a leading non-zero bit of an integer, shifts the integer such that the leading non-zero bit is the leftmost bit. A look-up table receives the shifted integer and provides a number representative of the mantissa portion of the logarithm of the shifted number. An encoder receives a Point Set Input value, a scale value for said integer, and the number of binary positions shifted and generates the exponential portion of the logarithm of the integer. For converting logarithmic representation of a number into integer representation, the apparatus has a look-up table which receives the mantissa component of the logarithmic representation and provides a first number. A decoder receives the exponential component of the logarithmic representation and a Point Set Output value, a scale value for said integer, and supplies a shifted signal. The shifted signal is supplied to a shifter along with the first number and the shifter shifts the first number by the shift signal to produce the integer.

5109524, Apr 28, 1992

Oct 28, 1988

7/263905

Lawrence F. Wagner - Berkeley CA
Korbin S. Van Dyke - Fremont CA
Wayne P. Burleson - Palo Alto CA
Robert D. Hemming - San Jose CA
John P. Guadagna - Morgan Hill CA

VLSI Technology, Inc. - San Jose CA

G06F 1576

395800

A digital processor has a controller, a data converter, a data register, and a logarithmic calculator. The processor has an address bus and a data bus for communication therewith. The address bus is connected to the controller. The data bus is connected to the controller and to the data register. Program instructions from the data bus are supplied to the controller and data on the data bus are supplied to the data register. Program instructions supplied to the controller are decoded and internal program instructions are generated by the controller. The controller communicates with the data converter, data register, and the logarithmic calculator via an internal bus through the internal program instructions. Integer data from the data bus are stored in the data register. The data converter receives the integer data, converts it into logarithmic data, and stores it in the data register.

4415767, Nov 15, 1983

Oct 19, 1981

6/312801

Stephen P. Gill - Atherton CA
Lawrence F. Wagner - Berkeley CA
Gregory G. Frye - San Leandro CA
Klaus-Peter A. Bantowsky - Hayward CA

Votan - Fremont CA

G10L 100

381 45

Speech signal analysis for data reduction, as stored for synthesis or recognition, is improved by features including: digital spectral analysis; reduction of channel data and bit allocation by selective summation of groups of contiguous data; using the mean average of the log amplitude to find the deviation for each channel; also using the instaneous shape of the mean value for each channel for pairs of adjacent frames, all combined to find a feature ensemble for each pair of adjacent frames.