Leah Elise Miller, 51Menlo Park, CA

6459049, Oct 1, 2002

Jun 20, 2001

09/885299

Leah M. Miller - Fremont CA
Farshad Ghahghahi - Los Gatos CA
Edwin M. Fulcher - Palo Alto CA
Aritharan Thurairajaratnam - Fremont CA

LSI Logic Corporation - Milpitas CA

H01R 909

174261, 257691, 361777

A structure for receiving electrical signals near a central portion of the structure and distributing the electrical signals to a peripheral portion of the structure. The structure has a first set of contacts arranged in an array near the central portion of the structure. Electrically conductive traces connect the first set of contacts to a second set of contacts, where each of the electrically conductive traces has at least a first segment, a second segment, and a third segment. The first segment of each of the electrically conductive traces has relatively narrow width and spacing. The first segment of each of the electrically conductive traces is connected on a first end of the first segment to one of the first set of contacts and on a second end of the first segment to the second segment of each of the electrically conductive traces. The second segment of each of the electrically conductive traces has relatively intermediate width and spacing. The second segment of each of the electrically conductive traces is connected on a first end of the second segment to the second end of the first segment and on a second end of the second segment to the third segment of each of the electrically conductive traces.

6534968, Mar 18, 2003

Aug 10, 2001

09/928071

Leah M. Miller - Fremont CA
Anand Govind - Fremont CA
Zafer Kutlu - Menlo Park CA
Chao-Wen Chung - Union City CA
Aritharan Thurairajaratnam - Fremont CA

LSI Logic Corporation - Milpitas CA

G01R 3100

3241581, 324500, 324537

An apparatus for detecting failures in electrical connections between an integrated circuit package substrate and a circuit board. The substrate has substrate electrical contacts that are electrically connected one to another in first sets in a first region of the substrate. The circuit board has circuit board electrical contacts that are electrically connected one to another in second sets in a second region of the circuit board. The substrate electrical contacts align with and make electrical contact with the circuit board electrical contacts. The first region of the substrate aligns with the second region of the circuit board when the substrate electrical contacts make electrical contact with the circuit board electrical contacts. The first sets of substrate electrical contacts form chains of electrical contacts with the second sets of circuit board electrical contacts. The chains of electrical contacts loop back and forth electrically between the substrate and the circuit board.

6680532, Jan 20, 2004

Oct 7, 2002

10/265751

Leah M. Miller - Fremont CA
Kishor Desai - Fremont CA

LSI Logic Corporation - Milpitas CA

H01L 2348

257723, 257706, 257709

A multi chip package, which includes a package substrate having a first side and an opposing second side. The first side is for receiving package electrical connections. Integrated circuits are electrically connected and structurally connected by their first sides to the second side of the package substrate. Heat spreaders are disposed adjacent the second side of the integrated circuits, where a single one of the heat spreaders is associated with a single one of the integrated circuits, but not all of the integrated circuits have an associated heat spreader. A single stiffener having a first side and an opposing second side covers all of the integrated circuits and heat spreaders, where the first side of the stiffener is disposed adjacent the second side of the heat spreaders.

6701270, Mar 2, 2004

Sep 20, 2001

09/957410

Leah M. Miller - Fremont CA
Anand Govind - Fremont CA

LSI Logic Corporation - Milpitas CA

G06F 1900

702117, 714724, 324500

The present invention provides a method for reliability testing leakage characteristics in an electronic circuit, and a testing device for accomplishing the same. In an advantageous embodiment, the method includes dividing conductors of an electronic circuit into at least first and second noninterleaved regions having at least two conductors each. The method further includes forming conductor nets by electrically connecting ones of the at least two conductors of the first region to ones of the at least two conductors of the second region then testing for electrical leakage in the conductor nets.

6744130, Jun 1, 2004

Jul 8, 2003

10/615063

Leah M. Miller - Fremont CA
Aritharan Thurairajaratnam - San Jose CA
Edwin M. Fulcher - Palo Alto CA

LSI Logic Corporation - Milpitas CA

H01L 2348

257700, 257691, 257692, 257782

A package substrate having separate routing layers for transmitter signals and receiver signals, which signals are routed in differential pairs. The differential pairs of signal routing lines are isolated between a separate ground plane for transmitter and receiver traces and dedicated power planes, where a single power plane is dedicated to a single differential pair of signal routing lines. In this manner, a high degree of electrical isolation exists not only between the transmitter signal traces and the receiver signal traces, which are on different layers, but also between different differential pairs of signal routing lines on the same layer, each of which has its own dedicated power plane. Thus, a very high speed core routing system can be designed in a package substrate that can then be adapted as necessary to support a broad range of different integrated circuit designs.

6762366, Jul 13, 2004

Apr 27, 2001

09/844530

Leah M. Miller - Fremont CA
Farshad Ghahghahi - Los Gatos CA
Edwin M. Fulcher - Palo Alto CA

LSI Logic Corporation - Milpitas CA

H05K 100

174250, 174255, 174262, 361792, 361803

A printed circuit board having contacts in a contact array of rows and columns. Groups of n columns of the contacts are electrically connected to n-1 columns of vias disposed interstitially in a via array between the n columns of the contacts. A major vertical routing channel is formed between adjacent groups of n columns of the contacts and the n-1 columns of vias. First electrical traces are electrically connected to a first number of the vias. The first electrical traces are routed to an outside edge of the via array through the major vertical routing channel.

6768386, Jul 27, 2004

Apr 22, 2003

10/420219

Leah M. Miller - Fremont CA

LSI Logic Corporation - Milpitas CA

H03H 700

331 1, 331246, 331247, 257691, 257698

A package substrate having a first layer adapted to received an integrated circuit, with electrically conductive contacts adapted to send and receive signals to and from the integrated circuit. The first layer includes a ground plane. A second layer is disposed underneath the first layer, and has electrically conductive traces, including a single ended clock signal trace and a set of two differential clock signal traces. The single ended clock signal trace and the set of two differential clock signal traces are substantially surrounded by grounded guard traces from all other electrically conductive traces on the second layer. A first electrically nonconductive layer is disposed between the first layer and the second layer.

6791177, Sep 14, 2004

May 12, 2003

10/435805

Leah M. Miller - Fremont CA
Aritharan Thurairajaratnam - San Jose CA
Edwin M. Fulcher - Palo Alto CA

LSI Logic Corporation - Milpitas CA

H01L 2352

257691, 257698

A package substrate is contemplated herein for reducing cross-talk for noise-sensitive signals. The package substrate includes noise-sensitive conductors adapted to receive the noise-sensitive signals. In one embodiment, the cross-sectional width of the noise-sensitive conductors is increased to reduce certain parasitic effects such as resistance and/or inductance. The package substrate also includes guard conductors which are arranged co-planar with and substantially parallel to the noise-sensitive conductors. A plurality of vias spaced equidistant from one another extends from a ground conductor to the guard conductors, providing a substantially uniform voltage across the guard conductors. The overall effect will reduce the inductive and capacitive cross-talk from neighboring signals and increase the signal integrity of noise-sensitive signals.