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Lee B Max, 782474 Avignon Cir, Santa Rosa, CA 95403

Lee Max Phones & Addresses

Santa Rosa, CA   

Sunnyvale, CA   

Sonoma, CA   

4622 Don Jose Dr, Tucson, AZ 85718    520-5290519   

6284 Squiredell Dr, San Jose, CA 95129    408-2523807   

6824 Squiredell Dr, San Jose, CA 95129   

Waikoloa, HI   

Santa Clara, CA   

Pima, AZ   

Hawi, HI   

Calabasas, CA   

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Lee Max Photo 39

Lee Barnabas Max

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Lee Max

Publications & IP owners

Us Patents

Method Of Operating A Solid State Power Amplifying Device

US Patent:
6529081, Mar 4, 2003
Filed:
Jun 8, 2000
Appl. No.:
09/590771
Inventors:
Douglas M. Macheel - San Jose CA
Peter B. Jones - Cupertino CA
Lee B. Max - San Jose CA
Assignee:
Zeta, division of Sierra Tech Inc. - San Jose CA
International Classification:
H03F 314
US Classification:
330307, 330 66
Abstract:
According to one embodiment, a circuit is disclosed. The circuit comprises a solid state power amplifying device, an input impedance matching circuit and an output impedance matching circuit coupled to the solid state amplifying device. The input impedance matching circuit includes an input pitchfork trace pattern. The output impedance matching circuit includes an output pitchfork trace pattern. The circuit further discloses an input bias circuit and an output bias circuit.

High Rigidity, Multi-Layered Semiconductor Package And Method Of Making The Same

US Patent:
2001003, Nov 8, 2001
Filed:
Jan 10, 2001
Appl. No.:
09/758088
Inventors:
Jeffrey Karker - Cazenovia NY, US
Lee Max - San Jose CA, US
Juan Sepulveda - Tucson AZ, US
Kirankumar Dalal - North Andover MA, US
Norbert Adams - Syracuse NY, US
International Classification:
H01L021/48
US Classification:
257/666000, 438/106000
Abstract:
The present invention provide a plurality of layered substrates for semiconductor packages. The substrates include, for example, a metal matrix composite layer and at least one carrier layer having a coefficient of thermal expansion and a thermal conductivity greater than the metal matrix composite. In the preferred embodiment, the metal matrix composite includes between approximately 50% to 95% refractory metal with the remainder copper. Suitable carrier layer materials include, for example, copper. So configured, the layered substrates provide improved rigidity and thermal characteristics for matching with ceramic materials.

Solid State Power Amplifying Device

US Patent:
2002001, Jan 31, 2002
Filed:
Sep 13, 2001
Appl. No.:
09/952588
Inventors:
Douglas Macheel - San Jose CA, US
Lee Max - San Jose CA, US
International Classification:
H01L021/4763
H01L023/48
H01L023/52
H01L029/40
US Classification:
438/650000
Abstract:
According to one embodiment, a solid state amplifying device is disclosed. The amplifying device comprises a first input bond pad and a first input connection bonded to the first input bond pad. The amplifying device also includes a second input bond pad and a second input connection bonded to the second input bond pad. An equivalent magnitude of current is supplied to the first and second input bond pads.

Method Of Operating A Solid State Power Amplifying Device

US Patent:
2003006, Apr 3, 2003
Filed:
Nov 5, 2002
Appl. No.:
10/288084
Inventors:
Douglas Macheel - San Jose CA, US
Peter Jones - Cupertino CA, US
Lee Max - San Jose CA, US
International Classification:
H03F003/14
US Classification:
330/307000
Abstract:
According to one embodiment, a circuit is disclosed. The circuit comprises a solid state power amplifying device, an input impedance matching circuit and an output impedance matching circuit coupled to the solid state amplifying device. The input impedance matching circuit includes an input pitchfork trace pattern. The output impedance matching circuit includes an output pitchfork trace pattern. The circuit further discloses an input bias circuit and an output bias circuit.

Soild State Power Amplifying Device

US Patent:
2003008, May 15, 2003
Filed:
Nov 12, 2002
Appl. No.:
10/292560
Inventors:
Douglas Macheel - San Jose CA, US
Lee Max - San Jose CA, US
International Classification:
H01L023/48
US Classification:
257/767000
Abstract:
According to one embodiment, a solid state amplifying device is disclosed. The amplifying device comprises a first input bond pad and a first input connection bonded to the first input bond pad. The amplifying device also includes a second input bond pad and a second input connection bonded to the second input bond pad. An equivalent magnitude of current is supplied to the first and second input bond pads.

Solid State Power Amplifying Device

US Patent:
2003008, May 15, 2003
Filed:
Nov 12, 2002
Appl. No.:
10/292769
Inventors:
Douglas Macheel - San Jose CA, US
Lee Max - San Jose CA, US
International Classification:
H01L023/48
US Classification:
257/767000
Abstract:
According to one embodiment, a solid state amplifying device is disclosed. The amplifying device comprises a first input bond pad and a first input connection bonded to the first input bond pad. The amplifying device also includes a second input bond pad and a second input connection bonded to the second input bond pad. An equivalent magnitude of current is supplied to the first and second input bond pads.

Package For Push-Pull Semiconductor Devices

US Patent:
4107728, Aug 15, 1978
Filed:
Jan 7, 1977
Appl. No.:
5/757716
Inventors:
Lee B. Max - Sunnyvale CA
Assignee:
Varian Associates, Inc. - Palo Alto CA
International Classification:
H01L 3902
H01L 2302
H01L 2312
US Classification:
357 80
Abstract:
A semiconductor package for containing two individual devices such that they may be externally connected in a push-pull relationship. Two transistors, each having an input and output pad are formed on the same dielectric wafer, in a spaced relationship with each other and a ground plane so as to form two separate transmission line paths. The transistors are wired either in a grounded emitter or grounded base configuration. A shunt inductor is formed by a metallized strip or lead bond from the collector of one transistor to the collector of the other transistor. This inductor reduces the influence of the parasitic capacitance in the equivalent output circuit of the transistors. Since the collectors of both transistors are at the same DC level it is not necessary to include a DC blocking capacitor in series with the inductor. This increases the reliability and the reproducibility of the circuit because bonding wires necessary in prior devices to connect the blocking capacitor in series with the output inductance is not necessary. This packaging technique increases the output impedance, decreases the internal losses, and increases the bandwidth when wired as a push-pull circuit.

Method For Bonding A Ceramic To A Metal With A Copper-Containing Shim

US Patent:
6056186, May 2, 2000
Filed:
Jul 9, 1997
Appl. No.:
8/881599
Inventors:
Joseph F. Dickson - Cazenovia NY
Lee Benat Max - San Jose CA
Jeffrey A. Karker - Cazenovia NY
Assignee:
Brush Wellman Inc. - Cleveland OH
International Classification:
B23K 3102
US Classification:
2281221
Abstract:
A method is provided for the bonding of ceramics to metals for the production of semiconductor packages. The method includes forming a copper-copper oxide eutectic on a substantially planar copper shim. The shim and its copper-copper oxide eutectic are placed in contact with a ceramic layer and metal layer. The assembly, so formed, is then heated to a temperature at least equal to the melting point of the eutectic and no greater than the melting temperature of copper. Upon cooling of the eutectic, a bond forms bond the ceramic layer to the metal layer.

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