Lei He, 32Rosemead, CA

7714610, May 11, 2010

Dec 4, 2006

11/566573

Lei He - Pasadena CA, US

The Regents of the University of California - Oakland CA

H03K 19/177

326 41, 326 38, 326 39, 326 40

Field Programmable Logic Arrays (FPGAs) are described which utilize multiple power supply voltages to reduce both dynamic power and leakage power without sacrificing speed or substantially increasing device area. Power reduction mechanisms are described for numerous portions of the FPGA, including logic blocks, routing circuits, connection blocks, switch blocks, configuration memory cells, and so forth. Embodiments describe circuits and methods for implementing multiple supplies as sources of V, multiple voltage thresholding V, signal level translators, and power gating of circuitry to deactivate portions of the circuit which are inactive. The supply voltage levels can be fixed, or programmable. Methods are described for performing circuit CAD in the routing and assignment process on FPGAs, in particular for optimizing FPGA use having the power reduction circuits taught. Routing methods describe utilizing slack timing, power sensitivity, trace-based simulations, and other techniques to optimize circuit utilization on a multi VFPGA.

7877719, Jan 25, 2011

Dec 10, 2007

11/953175

Lei He - Pasadena CA, US

The Regents of the University of California - Oakland CA

G06F 17/50
H03K 17/16
H03K 19/003
H01L 25/00

716 9, 716 10, 716 13, 716 14, 326 31, 326 41, 326101

Integrated circuit apparatus and methods are described for inserting multi-Vbuffers within an interconnection tree during routing toward minimization of power under a delay constraint. Insertion of level converters is not necessary within the routing trees of the interconnect tree despite the insertion of the multi-Vbuffers. Techniques are described for controlling the dramatic complexity increment due to simultaneous delay and power consideration and increased buffer choices. Overhead reduction techniques are taught including: sampling based techniques, prediction based pruning techniques (PSP) and (PMP), and escape grid reduction, each of which are directed to multi-Vbuffer insertion. The resultant integrated circuits are routed with substantial power reductions over conventional routing.

7921402, Apr 5, 2011

Dec 27, 2007

11/965483

Lei He - Pasadena CA, US

The Regents of the University of California - Oakland CA

G06F 17/50

716136, 716111, 716117, 716128, 703 16

Methods are described herein which consider both die-to-die and within-die variations in effective channel length, threshold voltage, and gate oxide thickness, based on first developing closed-form models of chip level FPGA leakage and timing variations. Execution times are significantly reduced using these methods in comparison to performing detailed evaluation. The teachings provide mean and standard deviation which were found to be within 3% from those computed by Monte Carlo simulation, while leakage and delay variations can be up to 3× and 1. 9×, respectively. Analytical yield models are derived which consider both leakage and timing variations, and use such models to evaluate FPGA device and architecture in response to process variations. The teachings allow improved modeling of leakage and timing yields and thus co-optimization to improve yield rates.

8595671, Nov 26, 2013

May 4, 2010

12/773686

Lei He - Irvine CA, US

The Regents of the University of California - Oakland CA

G06F 17/50

716116

Field Programmable Logic Arrays (FPGAs) are described which utilize multiple power supply voltages to reduce both dynamic power and leakage power without sacrificing speed or substantially increasing device area. Power reduction mechanisms are described for numerous portions of the FPGA, including logic blocks, routing circuits, connection blocks, switch blocks, configuration memory cells, and so forth. Embodiments describe circuits and methods for implementing multiple supplies as sources of V, multiple voltage thresholding V, signal level translators, and power gating of circuitry to deactivate portions of the circuit which are inactive. The supply voltage levels can be fixed, or programmable. Methods are described for performing circuit CAD in the routing and assignment process on FPGAs, in particular for optimizing FPGA use having the power reduction circuits taught. Routing methods describe utilizing slack timing, power sensitivity, trace-based simulations, and other techniques to optimize circuit utilization on a multi VFPGA.

2008007, Mar 20, 2008

Sep 19, 2007

11/858099

Lei He - Pasadena CA, US
Hao Yu - Glendale CA, US

THE REGENTS OF THE UNIVERSITY OF CALIFORNIA - Oakland CA

G06F 17/50
G06F 7/60

716002000, 703002000

Model-order reduction techniques are described for RLC circuits modeling the VLSI layouts. A structured model order reduction is developed to preserve the block-level sparsity, hierarchy and latency. In addition, a structured and parameterized model order reduction is developed to generate macromodels for design optimizations of VLSI layouts. The applications are thermal via allocation under the dynamic thermal integrity and via stapling to simultaneously optimize thermal and power integrity.