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Le N NguyenDanbury, CT

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Career records & work history

Medicine Doctors

Le K. Nguyen

Specialties:
Internal Medicine
Work:
Louisiana State University Health Care Network
3700 Saint Charles Ave, New Orleans, LA 70115
504-4121366 (phone) 504-4121367 (fax)
Education:
Medical School
Louisiana State University School of Medicine at New Orleans
Graduated: 2009
Procedures:
Electrocardiogram (EKG or ECG), Vaccine Administration
Conditions:
Acute Bronchitis, Acute Renal Failure, Anemia, Attention Deficit Disorder (ADD), Benign Prostatic Hypertrophy, Bipolar Disorder, Bronchial Asthma, Chronic Renal Disease, Contact Dermatitis, Depressive Disorders, Diabetic Peripheral Neuropathy, Gout, Hypertension (HTN), Infectious Liver Disease, Iron Deficiency Anemia, Malignant Neoplasm of Female Breast, Migraine Headache, Peripheral Nerve Disorders, Vitamin D Deficiency, Abnormal Vaginal Bleeding, Acne, Acute Conjunctivitis, Acute Pharyngitis, Acute Sinusitis, Acute Upper Respiratory Tract Infections, Alopecia Areata, Alzheimer's Disease, Anxiety Dissociative and Somatoform Disorders, Anxiety Phobic Disorders, Atopic Dermatitis, Atrial Fibrillation and Atrial Flutter, Benign Polyps of the Colon, Benign Thyroid Diseases, Candidiasis, Candidiasis of Vulva and Vagina, Cardiac Arrhythmia, Carpel Tunnel Syndrome, Chronic Bronchitis, Congenital Anomalies of the Heart, Constipation, Dementia, Dermatitis, Diabetes Mellitus (DM), Disorders of Lipoid Metabolism, Diverticulitis, Epilepsy, Erectile Dysfunction (ED), Fractures, Dislocations, Derangement, and Sprains, Gastritis and Duodenitis, Gastroesophageal Reflux Disease (GERD), Genital HPV, Glaucoma, Hearing Loss, Heart Failure, Hemolytic Anemia, Hemorrhagic stroke, Herpes Genitalis, Herpes Simplex, Herpes Zoster, HIV Infection, Hyperthyroidism, Hypothyroidism, Intervertebral Disc Degeneration, Irritable Bowel Syndrome (IBS), Ischemic Bowel Disease, Ischemic Heart Disease, Ischemic Stroke, Lateral Epicondylitis, Menopausal and Postmenopausal Disorders, Mitral Valvular Disease, Multiple Sclerosis (MS), Non-Toxic Goiter, Obstructive Sleep Apnea, Osteoarthritis, Osteomyelitis, Osteoporosis, Otitis Media, Overweight and Obesity, Parkinson's Disease, Paroxysmal Supreventricular Tachycardia (PSVT), Peptic Ulcer Disease, Plantar Fascitis, Polycystic Ovarian Syndrome (PCOS), Post Traumatic Stress Disorder (PTSD), Rheumatoid Arthritis, Sciatica, Sickle-Cell Disease, Skin and Subcutaneous Infections, Substance Abuse and/or Dependency, Tempromandibular Joint Disorders (TMJ), Tension Headache, Thyroiditis, Urinary Incontinence, Urinary Tract Infection (UT), Venous Embolism and Thrombosis, Vitamin B12 Deficiency Anemia
Languages:
English
Description:
Dr. Nguyen graduated from the Louisiana State University School of Medicine at New Orleans in 2009. She works in New Orleans, LA and specializes in Internal Medicine. Dr. Nguyen is affiliated with Touro Infirmary.

Le Nguyen

Specialties:
Urgent Care Medicine
Work:
Nextcare Urgent CarePrimaCare Urgent Care
9901 Royal Ln STE 106, Dallas, TX 75231
214-9020000 (phone) 214-9020002 (fax)
Site
Education:
Medical School
Med & Pharm Univ, Ho Chi Minh City, Viet Nam (840 01 Prior 1/71)
Graduated: 1992
Conditions:
Abdominal Hernia, Abnormal Vaginal Bleeding, Acne, Acute Bronchitis, Acute Conjunctivitis, Acute Pharyngitis, Acute Sinusitis, Acute Upper Respiratory Tract Infections, Allergic Rhinitis, Anemia, Anxiety Dissociative and Somatoform Disorders, Anxiety Phobic Disorders, Atopic Dermatitis, Atrial Fibrillation and Atrial Flutter, Bacterial Food Poisoning, Bacterial Pneumonia, Benign Paroxysmal Positional Vertigo, Benign Prostatic Hypertrophy, Bipolar Disorder, Breast Disorders, Bronchial Asthma, Burns, Calculus of the Urinary System, Candidiasis, Candidiasis of Vulva and Vagina, Cardiac Arrhythmia, Carpel Tunnel Syndrome, Cataract, Chickenpox, Chronic Bronchitis, Chronic Fatigue Syndrome, Chronic Sinusitis, Conduction Disorders, Constipation, Contact Dermatitis, Croup, Dermatitis, Diabetes Mellitus (DM), Disorders of Lipoid Metabolism, Diverticulitis, Epilepsy, Erectile Dysfunction (ED), Esophagitis, Fractures, Dislocations, Derangement, and Sprains, Gastritis and Duodenitis, Gastroesophageal Reflux Disease (GERD), Gastrointestinal Hemorrhage, Gingival and Periodontal Diseases, Gout, Hallux Valgus, Hemolytic Anemia, Hemorrhoids, Herpes Genitalis, Herpes Simplex, Herpes Zoster, Hypertension (HTN), Hypothyroidism, Infectious Mononucleosis, Inguinal Hernia, Insomnia, Intervertebral Disc Degeneration, Iron Deficiency Anemia, Irritable Bowel Syndrome (IBS), Lateral Epicondylitis, Malignant Neoplasm of Female Breast, Migraine Headache, Mitral Valvular Disease, Non-Toxic Goiter, Obstructive Sleep Apnea, Osteoarthritis, Osteoporosis, Otitis Media, Plantar Warts, Pneumonia, Psoriasis, Rosacea, Scoliosis or Kyphoscoliosis, Sexually Transmitted Diseases (STDs), Skin and Subcutaneous Infections, Substance Abuse and/or Dependency, Sunburn, Tempromandibular Joint Disorders (TMJ), Tension Headache, Tinea Pedis, Tinea Unguium, Transient Cerebral Ischemia, Uterine Leiomyoma, Varicose Veins, Venous Embolism and Thrombosis, Ventral Hernia, Vitamin D Deficiency
Languages:
English
Description:
Dr. Nguyen graduated from the Med & Pharm Univ, Ho Chi Minh City, Viet Nam (840 01 Prior 1/71) in 1992. He works in Dallas, TX and specializes in Urgent Care Medicine.

Le Thao Nguyen

Specialties:
Internal Medicine - Geriatrics
Work:
River Park Medical Clinic
2550 Riv Park Plz STE 110, Fort Worth, TX 76116
817-7311289 (phone) 817-7311291 (fax)
Languages:
English, Vietnamese
Description:
Ms. Nguyen works in Fort Worth, TX and specializes in Internal Medicine - Geriatrics. Ms. Nguyen is affiliated with Lifecare Hospitals Of Fort Worth and Texas Health Harris Methodist Hospital Fort Worth.
Le Nguyen Photo 1

Le Kim Nguyen

Specialties:
Internal Medicine

License Records

Le Thi Nguyen

Licenses:
License #: PST.018950 - Active
Issued Date: Sep 10, 2009
Expiration Date: Dec 31, 2017
Type: Pharmacist

Le Thi Nguyen

Licenses:
License #: 1210002597
Category: Nail Technician Temporary Permit

Le Thi Nguyen

Phone:
972-5337691
Licenses:
License #: 1108541 - Active
Category: Cosmetology Operator
Expiration Date: Jan 28, 2018

Le N Nguyen

Licenses:
License #: 3026192 - Expired
Issued Date: Aug 16, 1999
Expiration Date: Feb 22, 2001
Type: Manicurist Type 3

Le Hung Nguyen

Licenses:
License #: 729 - Expired
Category: Nail Technology
Issued Date: Jan 1, 2000
Effective Date: Jan 1, 2010
Expiration Date: Dec 31, 2009
Type: Nail Technician

Le Cham Nguyen Hoang

Licenses:
License #: 2575 - Expired
Category: Nail Technology
Issued Date: Sep 14, 2009
Effective Date: Feb 25, 2010
Expiration Date: Dec 31, 2009
Type: Nail Technician

Le Nguyen resumes & CV records

Resumes

Le Nguyen Photo 44

Le Nguyen - Spring Valley, CA

Work:
John's Incredible Pizza Co Sep 2013 to 2000
Fun World Floor & Redemption Counter Attendant
Party City - San Diego, CA Jun 2013 to Oct 2013
Cashier
Aspiranet - San Jose, CA Nov 2010 to May 2011
Youth Intervention
Milpitas Golfland - Milpitas, CA Jul 2007 to Nov 2010
Supervisor
Education:
Mission College - Santa Clara, CA Sep 2012 to Mar 2014
Associate of Arts in Liberal Arts
Le Nguyen Photo 45

Le Nguyen - Springfield, MA

Work:
Community Health Resources Dec 2014 to 2000
Residential Counselor
Osborn Correctional Institution Jan 2014 to May 2014
Intern
Cutchins 2011 to 2014
Residential Counselor
Osborn Correctional Institution 2008 to 2008
Inmate Volunteer Counselor
Education:
AMERICAN INTERNATIONAL COLLEGE 2014
BACHELOR OF ARTS in SCIENCE
SPRINGFIELD TECHNICAL COMMUNITY COLLEGE 2012
ASSOCIATES
Skills:
CPR/First Aid Certified
Le Nguyen Photo 46

Le Nguyen - San Jose, CA

Work:
Citibank Apr 2012 to 2000
Citigold Relationship Manager
JPMorgan Chase Bank - San Jose, CA Feb 2011 to Nov 2011
Assistant Branch Manager - Sales
JPMorgan Chase Bank - San Jose, CA Jul 2006 to Jan 2011
Licensed Personal Banker
Education:
UC Berkeley Extension - Berkeley, CA 2014 to 2015
Certificate of Financial Planning and Analysis
San Jose State University - San Jose, CA May 2009
B.S. in Business Administration
Le Nguyen Photo 47

Le Van Nguyen - Fremont, CA

Work:
The Best Connection Inc - San Jose, CA 2008 to 2010 Micrel Inc - San Jose, CA 2000 to 2008
Wafer Fab Operator
Acer America Inc - San Jose, CA 1998 to 2000
Le Nguyen Photo 48

Le Nguyen - Milpitas, CA

Work:
Intersil Corp - Milpitas, CA Dec 2006 to Jun 2012
Staff Test Engineer
Atrua Technology Inc - Campbell, CA Jul 2004 to Oct 2006
Sr. Staff Test Engineer
Adaptec, Inc - Milpitas, CA Nov 2002 to Jul 2004
IC Test Consultant
Mindspeed Tech - San Jose, CA Mar 2001 to Nov 2002
Sr. Staff Test Engineer
STM - San Jose, CA Jan 1999 to Mar 2001
Staff Test Engineer
Adaptec, Inc - Milpitas, CA Mar 1995 to Jan 1999
Staff Test Engineer
LOGIC DEVICES Inc - Sunnyvale, CA Oct 1990 to Mar 1995
Sr. Test Engineer
A.M.D Inc - Sunnyvale, CA Jul 1986 to Oct 1990
Sr. Test Engineer
National Semiconductor Corp - Santa Clara, CA Jun 1984 to Jul 1986
Test Development Engineer
Education:
San Jose State University - San Jose, CA
B.S.E.E.
Le Nguyen Photo 49

Le Nguyen - San Jose, CA

Work:
Concentric Medical Inc Feb 2012 to 2000
Manufacturing assembler
TriReme Medical Inc - Pleasanton, CA May 2011 to Feb 2012
Manufacturing assembler
Voyage Medical Inc - Redwood City, CA Sep 2009 to Jan 2011
Manufacturing assembler
SURGRX - Redwood City, CA Jan 2008 to Sep 2009
Manufacturing assembler
Education:
Mission College GE Program
Teaching Program
Le Nguyen Photo 50

Le Van Nguyen - Mountain House, CA

Work:
FormFactor Inc Aug 2011 to 2000
Sr. Production Supervisor - Wafer Fab MFG - D Shift
Sartorius-Stedim - A Biotech Company - Concord, CA Apr 2010 to May 2011
Develop operator and lead skill levels to achieve maximum results
Systron Donner Inc - Concord, CA Feb 2006 to Oct 2009
Wafer Fab Supervisor
Blue Coat Systems Inc - Sunnyvale, CA Mar 2000 to Sep 2005
Production Manager - Web Security & Network Management MFG
KLA-Tencor - San Jose, CA Oct 1995 to Mar 2000
Manufacturing Manager
LTX / Trillium Corporation - San Jose, CA Sep 1982 to Apr 1995
Sr. Test Supervisor, Swing Shift, of Semiconductor Test Equipment Company
Education:
Mission College - Santa Clara, CA May 1985
Associate of Science in Electronics Engineering
Hue University May 1979
B.A. in Math

Publications & IP owners

Us Patents

Execution Unit For Processing A Data Stream Independently And In Parallel

US Patent:
6401194, Jun 4, 2002
Filed:
Jan 28, 1997
Appl. No.:
08/790142
Inventors:
Le Trong Nguyen - Monte Sereno CA
Heonchul Park - Cupertino CA
Roney S. Wong - Sunnyvale CA
Ted Nguyen - Saratoga CA
Edward H. Yu - Newark CA
Assignee:
Samsung Electronics Co., Ltd. - Seoul
International Classification:
G06F 9302
US Classification:
712210, 712212, 712 7, 712 8, 712 9, 712 4, 708507, 708524, 708682, 708550, 710 65, 710 66, 710127, 710 50
Abstract:
A vector processor provides a data path divided into smaller slices of data, with each slice processed in parallel with the other slices. Furthermore, an execution unit provides smaller arithmetic and functional units chained together to execute more complex microprocessor instructions requiring multiple cycles by sharing single-cycle operations, thereby reducing both costs and size of the microprocessor. One embodiment handles 288-bit data widths using 36-bit data path slices. Another embodiment executes integer multiply and multiply-and-accumulate and floating point add/subtract and multiply operations using single-cycle arithmetic logic units. Other embodiments support 8-bit, 9-bit, 16-bit, and 32-bit integer data types and 32-bit floating data types.

Integrated Structure Layout And Layout Of Interconnections For An Instruction Execution Unit Of An Integrated Circuit Chip

US Patent:
6401232, Jun 4, 2002
Filed:
Jun 27, 2000
Appl. No.:
09/604419
Inventors:
Kevin R. Iadonato - San Jose CA
Le Trong Nguyen - Monte Sereno CA
Assignee:
Seiko Epson Corporation - Tokyo
International Classification:
G06F 1750
US Classification:
716 10, 712 26, 712201, 326 47, 326101, 327565
Abstract:
An integrated structure layout of functional blocks and interconnections for an integrated circuit chip. Data dependency comparator blocks are arranged in rows and columns. This arrangement defines layout regions between adjacent ones of the data dependency comparator blocks in the rows. Tag assignment logic blocks are coupled to the data dependency comparator blocks to receive dependency information. The tag assignment logic blocks are positioned in one or more of the layout regions so as to be integrated with the data dependency comparator blocks to conserve area on the semiconductor chip and to spatially define a channel in and substantially orthogonal to one or more of the rows. Register file port multiplexer blocks are coupled to output lines of the tag assignment logic block adjacent to the orthogonal channel to receive tag information and to pass the tag information to address ports of a register file.

Data Processing Device With Memory Coupling Unit

US Patent:
6405273, Jun 11, 2002
Filed:
Nov 13, 1998
Appl. No.:
09/192170
Inventors:
Rod G. Fleck - Mountain View CA
Klaus Oberlaender - San Jose CA
Gigy Baror - Ramat Gan, IL
Alfred Eder - Friedberg, DE
Le Trong Nguyen - Monte Sereno CA
Assignee:
Infineon Technologies North America Corp. - San Jose CA
International Classification:
G06F 1300
US Classification:
710131
Abstract:
A data processing unit is disclosed with a register file having a plurality of registers. A memory having a plurality of n-bit input/output ports, and a coupling unit for coupling the memory with the register file, a memory address and select unit for addressing the memory banks are provided. The coupling unit comprises a bus having a bus width of at least 2n-bits forming at least a first and second sub-bus, first couplers for coupling each memory bank or the register file selectively with one of the sub-busses, and second couplers for coupling the register file or the memory banks with the bus.

Multiprocessor Operation In A Multimedia Signal Processor

US Patent:
6425054, Jul 23, 2002
Filed:
Oct 10, 2000
Appl. No.:
09/685982
Inventors:
Le Trong Nguyen - Monte Sereno CA
Assignee:
Samsung Electronics Co., Ltd. - Kyungki-do
International Classification:
G06F 1208
US Classification:
711117, 711118
Abstract:
To achieve high performance at low cost, an integrated digital signal processor uses an architecture which includes both a general purpose processor and a vector processor. The integrated digital signal processor also includes a cache subsystem, a first bus and a second bus. The cache subsystem provides caching and data routing for the processors and buses. Multiple simultaneous communication paths can be used in the cache subsystem for the processors and buses. Furthermore, simultaneous reads and writes are supported to a cache memory in the cache subsystem.

Microprocessor Architecture Capable Of Supporting Multiple Heterogeneous Processors

US Patent:
6611908, Aug 26, 2003
Filed:
Jun 21, 2001
Appl. No.:
09/884943
Inventors:
Derek J. Lentz - Los Gatos CA
Yasuaki Hagiwara - Santa Clara CA
Te-Li Lau - Palo Alto CA
Cheng-Long Tang - San Jose CA
Le Trong Nguyen - Monte Sereno CA
Assignee:
Seiko Epson Corporation - Tokyo
International Classification:
G06F 1314
US Classification:
712 29, 710243, 710317
Abstract:
A memory control unit for controlling access, by one or more devices within a processor, to a memory array unit external to the processor via one or more memory ports of the processor. The memory control unit includes a switch network to transfer data between the one or more devices of the processor and the one or more memory ports of the processor. The memory control unit also includes a switch arbitration unit to arbitrate for the switch network, and a port arbitration unit to arbitrate for the one or more memory ports.

High-Performance, Superscalar-Based Computer System With Out-Of-Order Instruction Execution

US Patent:
6647485, Nov 11, 2003
Filed:
May 10, 2001
Appl. No.:
09/852293
Inventors:
Le Trong Nguyen - Monte Sereno CA
Derek J. Lentz - Los Gatos CA
Yoshiyuki Miyayama - Santa Clara CA
Sanjiv Garg - Freemont CA
Yasuaki Hagiwara - Santa Clara CA
Johannes Wang - Redwood City CA
Te-Li Lau - Palo Alto CA
Quang H. Trang - San Jose CA
Assignee:
Seiko Epson Corporation - Tokyo
International Classification:
G06F 930
US Classification:
712 23, 712206, 712207, 712245, 712219, 711169
Abstract:
A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.

Integrated Structure Layout And Layout Of Interconnections For An Instruction Execution Unit Of An Integrated Circuit Chip

US Patent:
6782521, Aug 24, 2004
Filed:
May 7, 2002
Appl. No.:
10/139318
Inventors:
Kevin R. Iadonato - San Jose CA
Le Trong Nguyen - Monte Sereno CA
Assignee:
Seiko Epson Corporation - Tokyo
International Classification:
G06F 1750
US Classification:
716 10, 716 14, 716 7, 326 47, 326101, 327565, 712 26, 712201
Abstract:
An integrated structure layout of functional blocks and interconnections for an integrated circuit chip. Data dependency comparator blocks are arranged in rows and columns. This arrangement defines layout regions between adjacent ones of the data dependency comparator blocks in the rows. Tag assignment logic blocks are coupled to the data dependency comparator blocks to receive dependency information. The tag assignment logic blocks are positioned in one or more of the layout regions so as to be integrated with the data dependency comparator blocks to conserve area on the semiconductor chip and to spatially define a channel in and substantially orthogonal to one or more of the rows. Register file port multiplexer blocks are coupled to output lines of the tag assignment logic block adjacent to the orthogonal channel to receive tag information and to pass the tag information to address ports of a register file.

High-Performance, Superscalar-Based Computer System With Out-Of-Order Instruction Execution

US Patent:
6915412, Jul 5, 2005
Filed:
Oct 30, 2002
Appl. No.:
10/283106
Inventors:
Le Trong Nguyen - Monte Sereno CA, US
Derek J. Lentz - Los Gatos CA, US
Yoshiyuki Miyayama - Santa Clara CA, US
Sanjiv Garg - Freemont CA, US
Yasuaki Hagiwara - Santa Clara CA, US
Johannes Wang - Redwood City CA, US
Te-Li Lau - Palo Alto CA, US
Quang H. Trang - San Jose CA, US
Assignee:
Seiko Epson Corporation - Tokyo
International Classification:
G06F015/76
G06F013/40
G06F009/38
G06F013/36
US Classification:
712 23, 712206, 712207, 712215, 712213, 712233, 712237, 712238, 712248, 712 41, 711125, 710 52, 710310
Abstract:
A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.

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