Danny LiLakewood, CA
Danny Li Phones & Addresses
Lakewood, CA
Monterey Park, CA
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Publications & IP owners
Us Patents
Method Of Fabricating A Self-Aligned Double Recess Gate Profile
US Patent:
5556797, Sep 17, 1996
Filed:
May 30, 1995
Appl. No.:
8/453676
Inventors:
Tom Y. Chi - San Gabriel CA
Liping D. Hou - Rancho Palos Verdes CA
Kusol Lee - Gardena CA
Danny Li - Torrance CA
Ishver K. Naik - Rancho Palos Verdes CA
Tom Quach - Torrance CA
Liping D. Hou - Rancho Palos Verdes CA
Kusol Lee - Gardena CA
Danny Li - Torrance CA
Ishver K. Naik - Rancho Palos Verdes CA
Tom Quach - Torrance CA
Assignee:
Hughes Aircraft Company - Los Angeles CA
International Classification:
H01L 218258
US Classification:
437405
Abstract:
A method of fabricating a self-aligned double gate recess profile in a semiconductor substrate is disclosed in which a first mask layer is formed over the substrate. A second mask layer having an opening is formed over the first mask layer. An opening at least as wide as the second mask layer's opening is formed through the first mask layer to expose the substrate beneath the second mask layer's opening. A first recess is etched in the semiconductor through the second mask layer's opening. The first mask layer's opening is then uniformly expanded and a wider recess, aligned to the first recess, is then formed in the semiconductor. The method is particularly applicable to the formation of self-aligned gate and channel recesses in a GaAs MESFET.
Dual Etchant Process, Particularly For Gate Recess Fabrication In Gaas Mmic Chips
US Patent:
5436201, Jul 25, 1995
Filed:
May 28, 1993
Appl. No.:
8/068871
Inventors:
Tom Y. Chi - San Gabriel CA
Danny Li - Torrance CA
Liping Hou - Rancho Palos Verdes CA
Tom Quach - Torrance CA
Danny Li - Torrance CA
Liping Hou - Rancho Palos Verdes CA
Tom Quach - Torrance CA
Assignee:
Hughes Aircraft Company - Los Angeles CA
International Classification:
H01L 218252
US Classification:
437203
Abstract:
A semiconductor substrate is etched in a two-step sequence, with two different liquid etchants that have different lateral etch rates. The relative time periods for which the etchants are applied are selected to achieve a close match between the actual etch profile and the desired profile. The process is particularly applicable to the formation of a gate recess in a GaAs MESFET for high power amplification.
Process For Providing Clean Lift-Off Of Sputtered Thin Film Layers
US Patent:
5705432, Jan 6, 1998
Filed:
Dec 1, 1995
Appl. No.:
8/566197
Inventors:
Kusol Lee - Gardena CA
Tom Quach - Torrance CA
Danny Li - Torrance CA
Liping D. Hou - Rancho Palos Verdes CA
Sam Chung - Costa Mesa CA
Tom Y. Chi - San Gabriel CA
Tom Quach - Torrance CA
Danny Li - Torrance CA
Liping D. Hou - Rancho Palos Verdes CA
Sam Chung - Costa Mesa CA
Tom Y. Chi - San Gabriel CA
Assignee:
Hughes Aircraft Company - Los Angeles CA
International Classification:
H01L 21465
US Classification:
437228
Abstract:
A unique photoresist process is provided which achieves clean and complete lift-off of a thin film layer such as a sputtered thin film formed on a photoresist which is formed above a semiconductor substrate. The process of the present invention relies on a reentrant photoresist profile which breaks the continuity of the thin film layer. Accordingly, the process of the present invention ensures a clean lift-off. The desired photoresist profile which breaks the continuity of the thin film layer can be obtained by a typical photoresist process preceded by an oxidation process that takes place on the surface of the semiconductor substrate. The oxidation process provides a thin native oxide layer with thickness ranging from about 30 to 50. ANG. No extra processing steps involving dielectric film deposition and etch are required to achieve clean lift-off. Nevertheless, the process of the present invention ensures the clean lift-off of the thin film layer.
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