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Hong Lin He, 753738 95Th St, Flushing, NY 11372

Hong He Phones & Addresses

3738 95Th St, Jackson Heights, NY 11372    718-2055930   

Jackson Hts, NY   

Work

Company: Salt lake community college - Salt Lake City, UT 2010 Position: Tutor

Education

School / High School: Utah State University- Logan, UT May 2010 Specialities: Bachelor of Science in Statistics

Skills

Relevant Skills: Experience with using R • SAS and Matlab Skilled with using MS Word • Excel • PowerPoint • MathCAD and Solid Edge Fluent in Mandarin Chinese and Shanghai dialect

Mentions for Hong Lin He

Hong He resumes & CV records

Resumes

Hong He Photo 25

Hong He

Hong He Photo 26

Hong He

Hong He Photo 27

Hong He

Hong He Photo 28

Hong He

Location:
United States
Hong He Photo 29

Hong Rachel He - Brooklyn, NY

Work:
Salt Lake Community College - Salt Lake City, UT 2010 to 2011
Tutor
Utah State University - Logan, UT 2009 to 2010
Grader
Utah State University - Logan, UT 2008 to 2010
Math and Statistics tutor
Salt Lake Community College - Salt Lake City, UT 2006 to 2007
Student Leadership Office, Office Assistant /Event Coordinator
Education:
Utah State University - Logan, UT May 2010
Bachelor of Science in Statistics
Columbia University - New York, NY
Master of Science in Actuarial Science
Skills:
Relevant Skills: Experience with using R, SAS and Matlab Skilled with using MS Word, Excel, PowerPoint, MathCAD and Solid Edge Fluent in Mandarin Chinese and Shanghai dialect

Publications & IP owners

Us Patents

Hybrid Aspect Ratio Trapping

US Patent:
2017019, Jul 6, 2017
Filed:
Mar 23, 2017
Appl. No.:
15/467821
Inventors:
- Armonk NY, US
Ramachandra Divakaruni - Ossining NY, US
Hong He - Albany NY, US
Juntao Li - Cohoes NY, US
International Classification:
H01L 29/10
H01L 29/04
H01L 29/78
H01L 21/28
H01L 29/161
Abstract:
A semiconductor structure includes a material stack located on a surface of a semiconductor substrate. The material stack includes, from bottom to top, a silicon germanium alloy portion that is substantially relaxed and defect-free and a semiconductor material pillar that is defect-free. A dielectric material structure surrounds sidewalls of the material stack and is present on exposed portions of the semiconductor substrate.

Hybrid Aspect Ratio Trapping

US Patent:
2016029, Oct 6, 2016
Filed:
Mar 30, 2015
Appl. No.:
14/672311
Inventors:
- Armonk NY, US
Ramachandra Divakaruni - Ossining NY, US
Hong He - Schenectady NY, US
Juntao Li - Cohoes NY, US
International Classification:
H01L 29/10
H01L 21/28
H01L 29/161
H01L 29/78
Abstract:
A semiconductor structure includes a material stack located on a surface of a semiconductor substrate. The material stack includes, from bottom to top, a silicon germanium alloy portion that is substantially relaxed and defect-free and a semiconductor material pillar that is defect-free. A dielectric material structure surrounds sidewalls of the material stack and is present on exposed portions of the semiconductor substrate.

Fin Field-Effect Transistors With Superlattice Channels

US Patent:
2015006, Mar 12, 2015
Filed:
Sep 11, 2013
Appl. No.:
14/023581
Inventors:
- Armonk NY, US
Bruce B. Doris - Slinerlands NY, US
Pouya Hashemi - White Plains NY, US
Hong He - Schenectady NY, US
Ali Khakifirooz - Mountain View CA, US
Alexander Reznicek - Troy NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 29/15
H01L 29/66
H01L 21/02
H01L 21/8234
US Classification:
257 19, 438283
Abstract:
FinFET structures may be formed including superlattice fins. The structure may include a superlattice fin of alternating layers of silicon-germanium with a germanium concentration of approximately 10% to 80% and a second semiconductor material. In some embodiments, the second semiconductor material may include either silicon or carbon-doped silicon. Where the second semiconductor material is carbon-doped silicon, the carbon concentration may range from approximately 0.2% to approximately 4%. The superlattice fin may have a height ranging from approximately 5 nm to approximately 100 nm and include between 5 and 30 alternating layers of silicon-germanium and the second semiconductor material. A gate may be formed over the superlattice fin and a source/drain region may be formed over an end of the superlattice fin.

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