Linlin LiuBrooklyn, NY
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Brooklyn, NY
Gloucester City, NJ
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Us Patents
Pin Photodiode Structure And Fabrication Process For Reducing Dielectric Delamination
US Patent:
7439599, Oct 21, 2008
Filed:
Mar 14, 2005
Appl. No.:
11/079708
Inventors:
Xiang Gao - Edison NJ, US
Alex Ceruzzi - Princeton Junction NJ, US
Steve Schwed - Bridgewater NJ, US
Linlin Liu - Hillsborough NJ, US
Mark Gottfried - Hillsborough NJ, US
Alex Ceruzzi - Princeton Junction NJ, US
Steve Schwed - Bridgewater NJ, US
Linlin Liu - Hillsborough NJ, US
Mark Gottfried - Hillsborough NJ, US
Assignee:
Emcore Corporation - Albuquerque NM
International Classification:
H01L 31/00
US Classification:
257443, 257458, 257466
Abstract:
A PIN photodiode, and a method of manufacturing a PIN photodiode that reduces dielectric delamination and increases device reliability. The process proceeds by forming an first type electrode layer on the substrate; forming an intrinsic layer of the first type electrode layer; forming a second type electrode layer on the intrinsic layer; etching the second type electrode layer to define a mesa shaped structure; and depositing a passivation material over the mesa shaped structure.
Pin Diode Structure With Zinc Diffusion Region
US Patent:
7538403, May 26, 2009
Filed:
Sep 19, 2005
Appl. No.:
11/230959
Inventors:
Xiang Gao - Edison NJ, US
Alex Ceruzzi - Princton Junction NJ, US
Linlin Liu - Hillsborough NJ, US
Stephen Schwed - Bridgewater NJ, US
Alex Ceruzzi - Princton Junction NJ, US
Linlin Liu - Hillsborough NJ, US
Stephen Schwed - Bridgewater NJ, US
Assignee:
Emcore Corporation - Albuquerque NM
International Classification:
H01L 27/15
US Classification:
257431, 257438, 257461, 257463, 257E31001
Abstract:
A PIN photodiode having a substrate, a first type electrode layer disposed on the substrate, a first layer of intrinsic material disposed over a portion of the first-type electrode layer, a first type window layer disposed over said intrinsic layer. An island shaped region of intrinsic material is disposed over the window layer and a dielectric layer disposed over the island region and at least the peripheral portion of said island shaped region whereby an opening is formed in the island shaped region. A dopant is diffused through the opening so as to form a PN junction that extends into the first layer of intrinsic material.
Pin Diode Structure With Zinc Diffusion Region
US Patent:
8022495, Sep 20, 2011
Filed:
Apr 8, 2009
Appl. No.:
12/420213
Inventors:
Xiang Gao - Edison NJ, US
Alex Ceruzzi - Princeton Junction NJ, US
Linlin Liu - Hillsborough NJ, US
Stephen Schwed - Bridgewater NJ, US
Alex Ceruzzi - Princeton Junction NJ, US
Linlin Liu - Hillsborough NJ, US
Stephen Schwed - Bridgewater NJ, US
Assignee:
Emcore Corporation - Albuquerque NM
International Classification:
H01L 31/06
US Classification:
257461, 257458, 257184, 257434, 257E31061
Abstract:
A PIN photodiode having a substrate, a first type electrode layer disposed on the substrate, a first layer of intrinsic material disposed over a portion of the first-type electrode layer, and a first type window layer disposed over the intrinsic layer. An island shaped region of intrinsic material is disposed over the window layer and a dielectric layer is disposed over the island region and at least the peripheral portion of said island shaped region whereby an opening is formed in the island shaped region. A dopant is diffused through the opening so as to form a PN junction that extends into the first layer of intrinsic material.
In Situ Grown Gate Dielectric And Field Plate Dielectric
US Patent:
2013014, Jun 13, 2013
Filed:
Dec 12, 2011
Appl. No.:
13/323672
Inventors:
John P. EDWARDS - Verona NJ, US
Linlin Liu - Hillsborough NJ, US
Linlin Liu - Hillsborough NJ, US
International Classification:
H01L 29/772
H01L 21/335
H01L 21/335
US Classification:
257192, 438172, 257E29242, 257E21403
Abstract:
Methods and apparatuses are disclosed for providing heterostructure field effect transistors (HFETs) with high-quality gate dielectric and field plate dielectric. The gate dielectric and field plate dielectric are in situ deposited on a semiconductor surface. The location of the gate electrode may be defined by etching a first pattern in the field plate dielectric and using the gate dielectric as an etch-stop. Alternatively, an additional etch-stop layer may be in situ deposited between the gate dielectric and the field plate dielectric. After etching the first pattern, a conductive material may be deposited and patterned to define the gate electrode. Source and drain electrodes that electrically contact the semiconductor surface are formed on opposite sides of the gate electrode.
High Quality Gan High-Voltage Hfets On Silicon
US Patent:
2013030, Nov 14, 2013
Filed:
Jul 17, 2013
Appl. No.:
13/944620
Inventors:
John P. EDWARDS - Verona NJ, US
Linlin LIU - Hillsborough NJ, US
Linlin LIU - Hillsborough NJ, US
International Classification:
H01L 21/02
US Classification:
438478
Abstract:
Substrates of GaN over silicon suitable for forming electronics devices such as heterostructure field effect transistors (HFETs), and methods of making the substrates, are disclosed. Voids in a crystalline AlOfilm on a top surface of a silicon wafer are formed. The top surface of the silicon wafer is along the silicon crystal orientation. A plurality of laminate layers is deposited over the voids and the AlOfilm. Each laminate layer includes an AN film and a GaN film. A transistor or other device may be formed in the top GaN film.
High-Quality Gan High-Voltage Hfets On Silicon
US Patent:
2015036, Dec 17, 2015
Filed:
Aug 24, 2015
Appl. No.:
14/834192
Inventors:
- San Jose CA, US
John P. Edwards - Verona NJ, US
Linlin Liu - Hillsborough NJ, US
John P. Edwards - Verona NJ, US
Linlin Liu - Hillsborough NJ, US
International Classification:
H01L 29/205
H01L 29/04
H01L 29/778
H01L 21/02
H01L 29/10
H01L 29/20
H01L 29/04
H01L 29/778
H01L 21/02
H01L 29/10
H01L 29/20
Abstract:
A GaN HFET includes a silicon substrate with an AlOlayer above the silicon substrate. The AlOlayer has voids formed therein. A plurality of alternating GaN and AlN layers are above the AlOlayer. The GaN and AlN layers are under continuous compressive stress.
High Quality Gan High-Voltage Hfets On Silicon
US Patent:
2014037, Dec 25, 2014
Filed:
Apr 18, 2014
Appl. No.:
14/256790
Inventors:
- San Jose CA, US
John P. EDWARDS - Verona NJ, US
Linlin LIU - Hillsborough NJ, US
John P. EDWARDS - Verona NJ, US
Linlin LIU - Hillsborough NJ, US
Assignee:
POWER INTEGRATIONS, INC. - San Jose CA
International Classification:
H01L 29/205
H01L 29/78
H01L 29/20
H01L 21/02
H01L 29/78
H01L 29/20
H01L 21/02
US Classification:
257 76
Abstract:
Substrates of GaN over silicon suitable for forming electronics devices such as heterostructure field effect transistors (HFETs), and methods of making the substrates, are disclosed. Voids in a crystalline AlOfilm on a top surface of a silicon wafer are formed. The top surface of the silicon wafer is along the silicon crystal orientation. A plurality of laminate layers is deposited over the voids and the AlOfilm. Each laminate layer includes an AlN film and a GaN film. A transistor or other device may be formed in the top GaN film.
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