Robert W Quan, 924324 Everett Ave, Oakland, CA 94602

7433981, Oct 7, 2008

Sep 30, 2005

11/243292

Robert Quan - San Francisco CA, US
Parthasarathy Sriram - San Jose CA, US

Nvidia Corporation - Santa Clara CA

G06F 13/12
G06F 7/38

710 65, 710 8, 712220, 713100

An architecture is described, wherein an operation unit, such as an arithmetic unit, is used for performing a variety of repetitive tasks. The present invention includes embodiments and related methods for power and computationally efficiency in performing repetitive tasks. The system includes an operation unit and a configuration control unit that is in communication with a processor. The processor sends the configuration information to the configuration unit and the configuration unit provides configuration information to the operation unit. The method includes configuring the operation unit using the configuration unit based on the configuration information, retrieving data from a designated location upon which the operation unit operates, and producing a result that is formatted and send to a destination.

2007007, Apr 5, 2007

Nov 14, 2006

11/599106

Partha Sriram - Los Altos CA, US
Robert Quan - San Francisco CA, US
Bhagawan Gnanapa - Hyderabad, IN
Ahmet Karakas - Palo Alto CA, US

G10L 21/00

704501000

In some embodiments, a data processing system including an operation unit including circuitry configurable to perform any selected one of a number of operations on data (e.g., audio data) and a configuration unit configured to assert configuration information to configure the operation unit to perform the selected operation. When the operation includes matrix multiplication of a data vector and a matrix whose coefficients exhibit symmetry, the configuration information preferably includes bits that determine signs of all but magnitudes of only a subset of the coefficients. When the operation includes successive addition and subtraction operations on operand pairs, the configuration information preferably includes bits that configure the operation unit to operate in an alternating addition/subtraction mode to perform successive addition and subtraction operations on each pair of data values of a sequence of data value pairs. In some embodiments, the configuration information includes bits that configure the operation unit to operate in a non-consecutive (e.g., butterfly or bit-reversed) addressing mode to access memory locations having consecutive addresses in a predetermined non-consecutive sequence. Other aspects are audio encoders and decoders including any embodiment of, and configuration units and operation units for use in, any embodiment of the system, and methods performed during operation of any embodiment of the system or configuration or operation unit thereof.