Maciej Bajkowski, 466208 Spicebrush Cv, Austin, TX 78759

7450454, Nov 11, 2008

May 9, 2007

11/746126

Maciej Bajkowski - Austin TX, US
Hamed Ghassemi - Austin TX, US
Huy B. Nguyen - Austin TX, US

Freescale Semiconductor, Inc. - Austin TX

G11C 7/00

365205, 365190, 365207

A data path of a memory is from an array of the memory, through a sense amplifier, through NOR gates, through N channel transistors, and through a latch that provides an output. The sense amplifier provides complementary data to the NOR gates which provide an output to the N channel transistors. The NOR gates provide outputs to the latch. This has the affect of providing outputs to gates of one inverter and drains of another inverter. Additional P channel transistors are in series with the inverters of the latch. The P channel transistor that is in series with the inverters whose drains are receiving the signal is made to be nonconductive by the output of the NOR gate to block current flow to the N channel transistor that is providing the input to the latch. The blocking of the current reduces the amount of current that the N channel transistor has to sink. This enables the N channel transistor, even at a reduced voltage, to be sufficiently conductive to flip the state of the latch.

7499342, Mar 3, 2009

Jan 5, 2007

11/620080

Maciej Bajkowski - Austin TX, US
Andrew Russell - Austin TX, US

Freescale Semiconductor, Inc. - Austin TX

G11C 7/10
G11C 7/06

36518905, 36518902, 36518907, 36518908

A dynamic module output device and methods thereof are disclosed. The dynamic module output device is connected to a dynamic module. The dynamic module output device provides the output of the dynamic module via two pathways. The first pathway is a direct output from the dynamic module. The second pathway includes a latch that stores the output of the dynamic module. The two output pathways are connected to a logic gate connected to downstream circuitry. Accordingly, data is provided to downstream circuitry rapidly via the first pathway, while being latched to allow the data to be available to the downstream circuitry after the evaluation phase. Such a parallel latching configuration provides enhanced efficiency in transfer and processing of information, especially in conjunction with utilization of precharge and evaluation phases.

8487657, Jul 16, 2013

May 31, 2012

13/484870

George P. Hoekstra - Austin TX, US
Maciej Bajkowski - Austin TX, US

Freescale Semiconductor, Inc. - Austin TX

H03K 19/096

326 98, 326112, 326121

A dynamic logic circuit includes an N channel transistor stack between a dynamic node and a first power supply terminal for receiving a plurality of logic signals. A P channel clock transistor is coupled between a second power supply terminal and the dynamic node is for receiving a clock signal. An N channel clock transistor is in series with the N channel stack and is between the dynamic node and the first power supply terminal is for receiving the clock signal. A keeper transistor has a first current electrode coupled to the dynamic node, a second current electrode coupled to a second power supply terminal, and a control electrode. A static logic circuit has an output for providing an output responsive to a state of the logic signals. The output is coupled to the control electrode of the keeper transistor.

7362134, Apr 22, 2008

Mar 24, 2006

11/388921

Maciej Bajkowski - Austin TX, US
George P. Hoekstra - Austin TX, US
Prashant U. Kenkare - Austin TX, US

Freescale Semiconductor, Inc. - Austin TX

H03K 19/20

326 46, 326104, 327407

A device includes a first combinatorial logic stage having a first input to receive a first data value, a second input to receive a bypass value and an output to provide one of a representation of the first data value or a first predetermined value based on the bypass value. The device further includes a latch stage having a first input to receive a second data value, a second input to receive the bypass value and an output to provide one of a latched representation of the second data value or a second predetermined value based on the bypass value. The device additionally includes a second combinatorial logic stage having a first input coupled to the output of the first combinatorial logic stage, a second input coupled to the output of the latch stage, and an output.

2008005, Mar 6, 2008

Aug 31, 2006

11/468815

Maciej Bajkowski - Austin TX, US
George P. Hoekstra - Austin TX, US
Hamed Ghassemi - Austin TX, US

H03L 5/00

327333

A level shifting circuit having a signal input that operates in a first voltage domain and a signal output that operates in a second voltage domain. In some embodiments, the level shifting circuit includes a clocked level shifter. In some embodiments, the level shifting circuit includes a level shifting latch that latches a translated output signal. In one example, the level shifting latch includes a latch portion and a stack of transistors with a transistor having a control electrode coupled to a clock input.

2013026, Oct 10, 2013

Oct 18, 2011

13/995434

Maciej Bajkowski - Austin TX, US
Giao N. Pham - Austin TX, US
Novat S. Nintunze - Portland OR, US
Hung C. Ngo - Austin TX, US

G11C 7/00
G06F 12/00

711154, 365189011

Methods and systems to provide bit cell write-assist, including equalization of voltages of Bit and nodes of a bit cell prior to a write operation. Equalization may be performed with a pulse-controlled transistor to transfer charge between the storage nodes. Pulse width and/or amplitude may be configurable, such as to scale with voltage. Bit cell write-assist may include reduction of bit cell retention strength during equalization, which may be continued during a write operation. Write-assist may be provided to each of multiple bit cells when a write operation is directed to a subset of the bit cells, which may conserve power and/or area. A partially-decoded address may be used to provide write-assistance to multiple bit cells prior to a write operation. Write-assistance may permit writing of Bit and with a voltage swing significantly lower than an operating voltage of the bit cell.

2020025, Aug 13, 2020

Jan 8, 2020

16/737655

- Austin TX, US
Subramanian RAMA - Austin TX, US
Maciej BAJKOWSKI - Austin TX, US

G06F 9/48
G06F 8/61
G06F 11/34
G06F 11/30

In a data processing system running at least one application on a hardware platform that includes at least one processor and a plurality of coprocessors, at least one kernel dispatched by an application is intercepted by an intermediate software layer running logically between the application and the system software. Compute functions are determined within kernel(s), and data dependencies are determined among the compute functions. The compute functions are dispatched to selected ones of the coprocessors based at least in part on the determined data dependencies and kernel results are returned to the application that dispatched the respective kernel.

2019021, Jul 11, 2019

Mar 16, 2019

16/355718

- Austin TX, US
Subramanian RAMA - Austin TX, US
Maciej BAJKOWSKI - Austin TX, US

Bitfusion.io, Inc. - Austin TX

G06F 9/54
G06F 11/14
G06F 9/455
G06F 9/50

An interface software layer is interposed between at least one application and a plurality of coprocessors. A data and command stream issued by the application(s) to an API of an intended one of the coprocessors is intercepted by the layer, which also acquires and stores the execution state information for the intended coprocessor at a coprocessor synchronization boundary. At least a portion of the intercepted data and command stream data is stored in a replay log associated with the intended coprocessor. The replay log associated with the intended coprocessor is then read out, along with the stored execution state information, and is submitted to and serviced by at least one different one of the coprocessors other than the intended coprocessor.