BackgroundCheck.run
Search For

Malcolm Ryle Dwyer, 46Volo, IL

Known as:
Malcolm R Dwyer Malcom R Dwyer Macolm R Dwyer
Related to:
William L Osterman 48

Malcolm Dwyer Phones & Addresses

Lindenhurst, IL   

12 Sandalwood Ct, Racine, WI 53402    262-6390322   

Glendale Heights, IL   

1443 Evergreen Dr, Palatine, IL 60074    847-7760912   

Mokena, IL   

Lindenhurst, IL   

Lane, IL   

Get Report
Control this profile

Mentions for Malcolm Ryle Dwyer

Malcolm Dwyer resumes & CV records

Resumes

Malcolm Dwyer Photo 15

Technology Architect - Front End

Location:
Chicago, IL
Industry:
Financial Services
Work:
Cme Group
Technology Architect - Front End Motorola Jul 1, 1999 - Dec 1, 2012
Principal Staff Engineer Purdue University 1996 - 1999
Computer Lab Assistant Robert Bosch May 1998 - Sep 1998
Engineering Intern
Education:
Purdue University 1995 - 1999
Bachelors, Bachelor of Science, Electrical Engineering
Skills:
Javascript, Jquery, Ios, User Experience Design, User Interface Design, Jquery Ui, Objective C, Graphic Design, Object Oriented Design, Embedded Systems, Photography, Perl, Linux, C++, Java, User Interface, Debugging, Embedded Linux, Embedded Software, Arm, System Architecture, Vhdl, Verilog, Android, Microcontrollers, Software Engineering, C, Python, Subversion, Ruby, Github, Mobile Devices, Algorithms, Testing, Css, Html 5
Malcolm Dwyer Photo 16

Malcolm Dwyer

Publications & IP owners

Us Patents

Virtual Memory Translation Unit For Multimedia Accelerators

US Patent:
7073041, Jul 4, 2006
Filed:
Oct 30, 2002
Appl. No.:
10/285153
Inventors:
Malcolm Ryle Dwyer - Glendale Heights IL, US
Nikolaos Bellas - Chicago IL, US
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
G06F 12/00
US Classification:
711203
Abstract:
A method and system for virtual memory translation of data represented in a multidimensional coordinate system when the physical memory may be located in more than one physical memory location. The translation of one or more virtual addresses into one or more accesses to one or more physical memories is achieved by representing each address of each element of a memory of the one or more physical memories as a point in a Cartesian coordinate system wherein consecutive points in the Cartesian coordinate system represent virtual memory addresses corresponding to elements from different physical memories of the one or more physical memories. Points in the Cartesian coordinate system are translated into one or more corresponding physical memory addresses, and read or write operations may be performed relative to these physical memory addresses. Multiple read or write operations may be performed during a single clock cycle through the use of parallel accesses of the one or more physical memories. Alternatively, multiple read or write operations may be performed in a pipelined architecture.

Automatic Generation Of Streaming Data Interface Circuit

US Patent:
7603492, Oct 13, 2009
Filed:
Sep 20, 2005
Appl. No.:
11/231171
Inventors:
Sek M. Chai - Streamwood IL, US
Nikos Bellas - Chicago IL, US
Malcolm R. Dwyer - Glendale Heights IL, US
Erica M. Lau - Schaumburg IL, US
Zhiyuan Li - Lake Zurich IL, US
Daniel A. Linzmeier - Wheeling IL, US
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
G06F 13/00
G06F 13/12
G06F 15/00
US Classification:
710 33, 710 8, 710 62, 710 72, 712 2, 712 7, 712 9
Abstract:
A streaming data interface device () of a streaming processing system () is automatically generated by selecting a set of circuit parameters () consistent with a set of circuit constraints and generating () a representation of a candidate memory interface device based upon a set of stream descriptors. The candidate streaming data interface device is evaluated () with respect to one or more quality metrics and the representation of the candidate streaming processor circuit is output () if the candidate memory interface device satisfies a set of processing system constraints and is better in at least one of the one or more quality metrics than other candidate memory interface devices.

System And Method For Parallel Computation Of An Array Transform

US Patent:
7634159, Dec 15, 2009
Filed:
Dec 8, 2004
Appl. No.:
11/007142
Inventors:
Malcolm R. Dwyer - Glendale Heights IL, US
James E. Crenshaw - Palatine IL, US
Zhiyuan Li - Lake Zurich IL, US
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
G06K 9/60
US Classification:
382307, 712 10, 712 16, 382281
Abstract:
An array transform system for parallel computation of a plurality of elements of an array transform includes a memory for storing an array of data elements. Each column of data elements from the memory is copied to a shifter that shifts the column of data elements in accordance with a shift value to produce a shifted column of data elements. The shifted columns of data elements are accumulated in a plurality of accumulators, with each accumulator producing an element of the array transform. A controller controls the shift value dependent upon the position of the column of data elements in the array of data elements.

Method And Apparatus For Configuring Buffers For Streaming Data Transfer

US Patent:
7802005, Sep 21, 2010
Filed:
Mar 30, 2007
Appl. No.:
11/694523
Inventors:
Sek M Chai - Streamwood IL, US
Nikos Bellas - Chicago IL, US
Malcolm R Dwyer - Glendale Heights IL, US
Daniel A Linzmeier - Wheeling IL, US
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
G06F 15/16
US Classification:
709231, 711170
Abstract:
A specification of a configurable processor is generated by generating (1) specifications of first and second stream memory interfaces to be operable to access data in accordance with first and second stream descriptors, and (2) a specification of an interim data storage device (buffer) to be accessed by the first and second stream memory interfaces and to be operable to receive data from a first computational module via the first stream memory interface and to transfer data to a second computational module via the second stream memory interface. The specifications are output and may be used to configure a configurable processor.

Method And Apparatus For Transforming A Non-Linear Lens-Distorted Image

US Patent:
8326077, Dec 4, 2012
Filed:
Oct 31, 2008
Appl. No.:
12/262363
Inventors:
Sek M. Chai - Streamwood IL, US
Malcolm R. Dwyer - Glendale Heights IL, US
Daniel A. Linzmeier - Wheeling IL, US
Nikolaos Bellas - Volos, GR
Assignee:
General Instrument Corporation - Horsham PA
International Classification:
G06K 9/40
US Classification:
382275
Abstract:
A method and apparatus for image processing a lens-distorted image (e. g. , a fisheye image) is provided. The method includes partitioning coordinate points in a selected output image into tiles. The output image is an undistorted rendition of a subset of the lens-distorted image. Coordinate points on a border of the tiles in the output image are selected. For each tile, coordinate points in the lens-distorted image corresponding to each selected coordinate point in the output image are calculated. In addition, for each tile, a bounding box on the lens-distorted image is selected. The bounding box includes the calculated coordinates in the lens-distorted image. The bounding boxes are expanded so that they encompass all coordinate points in the lens-distorted image that map to all coordinate points in their respective corresponding tiles. Output pixel values are generated for each tile from pixel values in their corresponding expanded bounding boxes.

Programmable Motion Estimation Module With Vector Array Unit

US Patent:
2003017, Sep 18, 2003
Filed:
Dec 7, 2001
Appl. No.:
10/006464
Inventors:
Nikolaos Bellas - Schaumburg IL, US
Malcolm Dwyer - Palatine IL, US
International Classification:
H04N009/64
US Classification:
348/699000, 375/240160, 375/240240, 375/240120
Abstract:
A programmable motion estimation module for processing pixel values from a sequence of digital video images. The module includes a programmable microcontroller, scalar and control register files, arithmetic logic units, a direct memory access unit and a vector array processor. The vector array processor includes a series of processing elements, a memory subsystem for storing pixel values and a crossbar switch for distributing pixel values from the memory subsystem to the processing elements. The module provides a flexible platform that can be programmed to implement a variety of different Motion Estimation (ME) algorithms using an associated Instruction Set Architecture without the need to modify the hardware.

Automated Configuration Of A Processing System Using Decoupled Memory Access And Computation

US Patent:
2008012, May 22, 2008
Filed:
Nov 20, 2006
Appl. No.:
11/561486
Inventors:
Sek M. Chai - Streamwood IL, US
Nikos Bellas - Chicago IL, US
Malcolm R. Dwyer - Glendale Heights IL, US
Daniel A. Linzmeier - Wheeling IL, US
Assignee:
MOTOROLA, INC. - Schaumburg IL
International Classification:
G06F 9/00
US Classification:
713 1
Abstract:
A method and system for automatic configuration of processor hardware from an application program that has stream descriptor definitions, descriptive of memory access locations, data access thread definitions having a stream descriptor and a data channel source or sink as parameters, and computation thread definitions having a function pointer, a data channel source and a data channel sink as parameters. The application program is compiled to produce a description of the data flow between the threads as specified in the application program. The hardware is configured to have streaming memory interface devices operable to access a memory in accordance with the stream descriptor definitions, data path devices operable to process data in accordance with the computation thread definitions and data channels operable to connect the data path devices and streaming memory interface devices in accordance with the description of the data flow.

Method And Apparatus For Transforming A Non-Linear Lens-Distorted Image

US Patent:
2013005, Mar 7, 2013
Filed:
Nov 2, 2012
Appl. No.:
13/667604
Inventors:
GENERAL INSTRUMENT CORPORATION - Horsham PA, US
Malcolm R. Dwyer - Glendale Heights IL, US
Daniel A. Linzmeier - Wheeling IL, US
Nikolas Bellas - Chicago IL, US
Assignee:
GENERAL INSTRUMENT CORPORATION - Horsham PA
International Classification:
G06K 9/40
US Classification:
382255
Abstract:
A method and apparatus for image processing a lens-distorted image (e.g., a fisheye image) is provided. The method includes partitioning coordinate points in a selected output image into tiles. The output image is an undistorted rendition of a subset of the lens-distorted image. Coordinate points on a border of the tiles in the output image are selected. For each tile, coordinate points in the lens-distorted image corresponding to each selected coordinate point in the output image are calculated. In addition, for each tile, a bounding box on the lens-distorted image is selected. The bounding box includes the calculated coordinates in the lens-distorted image. The bounding boxes are expanded so that they encompass all coordinate points in the lens-distorted image that map to all coordinate points in their respective corresponding tiles. Output pixel values are generated for each tile from pixel values in their corresponding expanded bounding boxes.

Possible Relatives

David R Dwyer  D L Dwyer  Dawn M Dwyer  Dean F Dwyer  Deanna L Dwyer  Dale M Dwyer  Deborah N Dwyer  Malcolm P Johnson  Malcolm W Johnston  Malcolm J Jones 

NOTICE: You may not use BackgroundCheck or the information it provides to make decisions about employment, credit, housing or any other purpose that would require Fair Credit Reporting Act (FCRA) compliance. BackgroundCheck is not a Consumer Reporting Agency (CRA) as defined by the FCRA and does not provide consumer reports.