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Manish A Arora, 53750 SW 9Th Ave APT 1708, Portland, OR 97205

Manish Arora Phones & Addresses

750 SW 9Th Ave APT 1708, Portland, OR 97205   

San Jose, CA   

Cumming, GA   

2701 Calvert St, Washington, DC 20008    202-2499457    202-5187193   

2701 Calvert St NW APT 824, Washington, DC 20008   

Hermosa Beach, CA   

Campbell, CA   

San Francisco, CA   

Hillsboro, OR   

Work

Company: Annik technology services pvt ltd 2009 Position: Sr. technical consultant

Education

School / High School: Kurukshetra University- Kurukshetra, HARYANA, IN Jul 2003 Specialities: Master in Computer Applications

Languages

English

Mentions for Manish A Arora

Career records & work history

Medicine Doctors

Manish Arora Photo 1

Dr. Manish Arora, Washington DC - MD (Doctor of Medicine)

Specialties:
Internal Medicine
Address:
50 Irving St Nw, Washington, DC 20422
202-7458357 (Phone)
Languages:
English

Manish Arora

Specialties:
Gastroenterology
Work:
Decatur Digestive Diseases
2828 Hwy 31 S STE 117, Decatur, AL 35603
256-3512116 (phone) 256-3512128 (fax)
Education:
Medical School
Gov't Med Coll, Guru Nanak Dev Univ, Amritsar, Punjab, India
Graduated: 2002
Languages:
English
Description:
Dr. Arora graduated from the Gov't Med Coll, Guru Nanak Dev Univ, Amritsar, Punjab, India in 2002. He works in Decatur, AL and specializes in Gastroenterology. Dr. Arora is affiliated with Decatur Morgan Hospital.
Manish Arora Photo 2

Manish Sarthi Arora

Specialties:
Internal Medicine
Neurology
Education:
M.S. Ramaiah Medical College (2000)

Manish Arora resumes & CV records

Resumes

Manish Arora Photo 39

Head Of Engagement & Delivery ( Acting) At Cable & Wireless Communications

Position:
Head of Engagement & Delivery ( Acting) at Cable & Wireless Communications, Program Manager at Cable & Wireless Communications
Location:
East Barnet, Greater London, United Kingdom
Industry:
Telecommunications
Work:
Cable & Wireless Communications - London, United Kingdom since Apr 2013
Head of Engagement & Delivery ( Acting)
Cable & Wireless Communications - London, United Kingdom since Jan 2013
Program Manager
Dhiraagu - Male' , Maldives Jan 2011 - Jan 2013
Director Information Systems
Bharti Airtel - Gurgaon , India May 2007 - Jan 2011
DGM - IT (Program Manager)
Bharti Airtel Limited - Shimla Area, India Nov 2005 - May 2007
IT Head
ANZBankTechnical Support Group May 2004 - Oct 2005
Support Team Lead
Gurgaon Feb 2003 - Apr 2004
Microsoft Technical Support
Dator A/S Software Developer Jun 1999 - Dec 2000
Software Developer
Education:
PMI ® 2010 - 2010
Project Management Professional (PMP)®, Project Management
XLRI Jamshedpur 2010 - 2010
PGCBM, Executive Education
IIM Bangalore - 2006 2006 - 2006
Executive Education, Managing Technology Outsourcing
RMIT University 2000 - 2001
MTech, Information technology
University of Rajasthan, Jaipur 1995 - 1998
B.Com, Business
Manish Arora Photo 40

Senior Analyst At Goldman Sachs

Position:
Senior Analyst at Goldman Sachs
Location:
Jersey City, New Jersey
Industry:
Information Technology and Services
Work:
Goldman Sachs - Jersey City since May 2013
Senior Analyst
Knight Capital Group - Jersey City Jun 2010 - May 2013
Assistant Vice President
Infosys Technologies Ltd Sep 2006 - Jun 2010
Technolgy Analyst
Education:
New York University 2011 - 2013
Master of Science (M.S.), Enterprise Risk Management
Kurukshetra University 2002 - 2006
B.Tech, Computer Science
Financial Risk Manager - Part I Candidate
Risk
Interests:
New Technologies, Investment Banking, Credit & Market Risk
Honor & Awards:
MVP 2008
Manish Arora Photo 41

Tech Lead At Tata Communications

Position:
Tech Lead at Tata Communications
Location:
Edison, New Jersey
Industry:
Telecommunications
Work:
Tata Communications - Matawan, NJ since Mar 2012
Tech Lead
Niksun - 100 Nassu Park Blvd, Princeton, NJ May 2011 - Mar 2012
Director
SES ASTRA Mar 2011 - May 2011
Consultant
Verizon Wireless Sep 2010 - Mar 2011
Consultant
Telcordia Technologies Oct 2008 - Sep 2010
Consultant
Ulticom Jan 2007 - Oct 2008
Senior Software Engineer, IMS/SIP Gateways
Motorola May 2005 - Jun 2006
Senior Software Engineer
Telcordia Technologies Feb 2001 - May 2005
Software Engineer
Education:
Stevens Institute of Technology 2004 - 2009
Masters, Telecommunication Mangement
Michigan State University 1998 - 2000
Bachleors, Computer Engineering
Washtenaw Community College 1995 - 1998
Associate
Skills:
SS7, Unix, SIP, Software Development, Diameter, Mobile Applications, Core Network, Technical Leadership, LTE, IP Multimedia Subsystem, Architectural Design, Team Leadership, High Availability, Agile Methodologies, Telecommunications, Wireless Networking, VoIP, Cloud Computing, C, Subversion, Java Enterprise Edition, UML, Solaris, Testing, Eclipse, Integration, Java, Software Engineering, GSM
Manish Arora Photo 42

Manish Arora

Location:
United States
Manish Arora Photo 43

Manish Arora

Location:
United States
Manish Arora Photo 44

Manish Arora

Location:
United States
Manish Arora Photo 45

Drilling At Dolphin International Ltd

Location:
United States
Industry:
Oil & Energy
Manish Arora Photo 46

Manish Arora

Location:
United States

Publications & IP owners

Us Patents

Method And Apparatus For Managing Power In A Thermal Couple Aware System

US Patent:
2017026, Sep 21, 2017
Filed:
Mar 16, 2016
Appl. No.:
15/071643
Inventors:
- Sunnyvale CA, US
Manish Arora - Sunnyvale CA, US
Abhinandan Majumdar - Ithaca NY, US
Indrani Paul - Austin TX, US
Leonardo de Paula Rosa Piga - Austin TX, US
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
G06F 1/20
G06F 1/32
Abstract:
A method and apparatus for managing power in a thermal couple aware system includes determining a candidate configuration mapping based upon one or more criteria, the candidate configuration mapping being a mapping of performance for a candidate configuration of processor sockets in the thermal couple aware system. The candidate configuration mapping is evaluated by comparing the candidate configuration mapping to a stored configuration. If the evaluated candidate configuration mapping provides a better metric than the stored configuration, the stored configuration is updated with the evaluated candidate configuration mapping, and programming instructions are executed in accordance with the candidate configuration mapping if no other configuration mappings are to be determined.

Determining Thermal Time Constants Of Processing Systems

US Patent:
2017022, Aug 3, 2017
Filed:
Jan 29, 2016
Appl. No.:
15/010965
Inventors:
- Sunnyvale CA, US
Manish Arora - Sunnyvale CA, US
Indrain Paul - Austin TX, US
Wei Huang - Austin TX, US
Srilatha Manne - Bellevue WA, US
International Classification:
G05B 19/404
Abstract:
A processing system includes one or more processing units to perform operations and one or more sensors to measure a temperature concurrently with the one or more processing units performing the operations. The processing system also includes a controller to receive feedback indicating the temperature and to determine a peak temperature and a thermal time constant for heating of the processing system based on a comparison of the measured temperature to a first temperature that is predicted based on the peak temperature and a previously determined thermal time constant for heating. Some embodiments of the controller can control a performance state of the processing system based on the peak temperature and the thermal time constant for heating of the processing system.

Thermally-Aware Throttling In A Three-Dimensional Processor Stack

US Patent:
2017008, Mar 23, 2017
Filed:
Sep 22, 2015
Appl. No.:
14/862044
Inventors:
- Sunnyvale CA, US
Manish Arora - Sunnyvale CA, US
Yasuko Eckert - Bellevue WA, US
Indrani Paul - Austin TX, US
International Classification:
G06F 1/20
G06F 1/32
G06T 1/20
Abstract:
A three-dimensional (3-D) processor stack includes a plurality of processor cores implemented in a plurality of layers. A controller is to selectively throttle one or more of a plurality of processor cores in response to detecting a thermal event. The controller selectively throttles the one or more of the plurality of processor cores based on values of thermal couplings between the plurality of layers and based on measures of criticality of threads executing on the plurality of processor cores.

Power Management For Heterogeneous Computing Systems

US Patent:
2017008, Mar 23, 2017
Filed:
Sep 17, 2015
Appl. No.:
14/857574
Inventors:
- Sunnyvale CA, US
Manish Arora - Sunnyvale CA, US
Indrani Paul - Austin TX, US
International Classification:
G06F 1/32
Abstract:
A computing system includes a set of computing resources and a datastore to store information representing a corresponding idle power consumption metric and a corresponding peak power consumption metric for each computing resource of the set. The computing system further includes a controller coupled to the set of computing resources and the datastore. The controller is to configure the set of computing resources to meet a power budget constraint for the set based on the corresponding idle power consumption metric and the corresponding peak power consumption metric for each computing resource of the set.

Control Of Thermal Energy Transfer For Phase Change Material In Data Center

US Patent:
2016033, Nov 17, 2016
Filed:
May 12, 2015
Appl. No.:
14/709655
Inventors:
- Sunnyvale CA, US
Manish Arora - Dublin CA, US
Wayne P. Burleson - Shutesbury MA, US
Indrani Paul - Round Rock TX, US
Yasuko Eckert - Bellevue WA, US
International Classification:
H05K 7/20
Abstract:
A cooling system controller for a set of computing resources of a data center includes a first interface to couple to a first flow controller that controls a rate of thermal energy transfer to a PCM store from the set of computing resources, a second interface to couple to a second flow controller that controls a rate of thermal energy transfer from the PCM store to a cooling system, and a controller to determine a current set of operational parameters for the data center and to manipulate the first and second flow controllers and via the first and second interfaces to control a net thermal energy transfer to and from the PCM store based on the current set of parameters.

Power And Performance Management Of Asynchronous Timing Domains In A Processing Device

US Patent:
2016007, Mar 17, 2016
Filed:
Sep 17, 2014
Appl. No.:
14/489130
Inventors:
- Sunnyvale CA, US
Manish Arora - Dublin CA, US
Indrani Paul - Round Rock TX, US
Yasuko Eckert - Kirkland WA, US
International Classification:
G06F 1/08
G06F 1/26
Abstract:
A processing device includes a producing processor unit in a first timing domain and a consuming processor unit in a second timing domain that is asynchronous with the first timing domain. A queue is used to convey data between the producing processor unit and the consuming processor unit. A system management unit is to modify one or both of an operating frequency or an operating voltage of one or both of the producing processor unit or the consuming processor unit based on a rate of change of a fullness of the queue.

Interface To Expose Interrupt Times To Hardware

US Patent:
2016007, Mar 17, 2016
Filed:
Sep 17, 2014
Appl. No.:
14/488864
Inventors:
- Sunnyvale CA, US
Manish Arora - Dublin CA, US
International Classification:
G06F 1/32
Abstract:
A power management controller is used to control power management states of a processing device. A register stores a timer tick value accessible to the power management controller. The timer tick value indicates when an interrupt is to occur in the processing device. The power management controller may use the exposed timer tick value to decide whether to transition between power management states such as an active state, an idle state, and a power-gated state. The timer tick value stored in the register may be modified by an operating system, an application, or software implemented on the processing device.

Predictive Management Of Heterogeneous Processing Systems

US Patent:
2016007, Mar 17, 2016
Filed:
Sep 17, 2014
Appl. No.:
14/488874
Inventors:
- Sunnyvale CA, US
Manish Arora - Dublin CA, US
Indrani Paul - Round Rock TX, US
Wayne P. Burleson - Shutesbury MA, US
International Classification:
G06F 9/48
G06N 5/02
Abstract:
A heterogeneous processing device includes one or more relatively large processing units and one or more relatively small processing units. The heterogeneous processing device selectively activates a large processing unit or a small processing unit to run a process thread based on a predicted duration of an active state of the process thread.

Isbn (Books And Publications)

Motor Accident Claims: Law &Amp; Procedure

Author:
Manish Arora
ISBN #:
8175340894

Bail: Law And Procedures, With Tips To Avoid Police Harassment

Author:
Manish Arora
ISBN #:
8185200858

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