Marcus Grindstaff resumes & CV records
Resumes
Marcus Grindstaff
Location:
Sacramento, California Area
Industry:
Health, Wellness and Fitness
Marcus A Grindstaff, 501070 Brock Cir, Folsom, CA 95630
Marcus Grindstaff Phones & Addresses
1061 Brock Cir, Folsom, CA 95630 916-9858464
314 Baird Dr, Folsom, CA 95630
Nampa, ID
Granite Bay, CA
8237 Woodlake Hills Dr, Orangevale, CA 95662
Sacramento, CA
Davis, CA
Mentions for Marcus A Grindstaff
Publications & IP owners
Us Patents
System For Correlating Clock Flight Times And Method Of Using
US Patent:
7062669, Jun 13, 2006
Filed:
Jun 21, 2002
Appl. No.:
10/177212
Inventors:
Marcus A. Grindstaff - Folsom CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 1/10
US Classification:
713500, 326 93, 375354
Abstract:
A system correlates clock signal flight times between a device on a board and a device on a card that is coupled to the board. A board device first trace runs from a clock driver on the board to the card. A board device second trace runs back to the board device.
System With Local Unified Memory Architecture And Method
US Patent:
7106339, Sep 12, 2006
Filed:
Apr 9, 2003
Appl. No.:
10/410080
Inventors:
Marcus Grindstaff - Folsom CA, US
Jeremy Burr - Portland OR, US
Jeremy Burr - Portland OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 12/02
G06F 15/167
G06F 15/167
US Classification:
345543, 345541, 345542
Abstract:
Local memory associated with one or more companion devices within a system is mapped into a system memory for use by an application processor.
Low Power Display Refresh
US Patent:
7734943, Jun 8, 2010
Filed:
Apr 3, 2003
Appl. No.:
10/407758
Inventors:
Rochelle J. Whelan - Portland OR, US
Marcus Grindstaff - Folsom CA, US
Marcus Grindstaff - Folsom CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 1/32
US Classification:
713324, 713320
Abstract:
An application processor coupled to a Static Random Access Memory (SRAM) interfaces with a graphics accelerator. A Dynamic Random Access Memory (DRAM) stores frame buffer data that may be transferred to a display through a switch located on the graphics accelerator in normal operation. In a power savings mode, the DRAM may be powered down and a copied frame buffer data stored in the SRAM may be transferred to the display through the switch.
Accelerated Dual-Display
US Patent:
2005013, Jun 23, 2005
Filed:
Dec 23, 2003
Appl. No.:
10/746486
Inventors:
Marcus Grindstaff - Folsom CA, US
Lawrence Booth - Phoenix AZ, US
Lawrence Booth - Phoenix AZ, US
International Classification:
G09G001/06
G09G005/00
G09G005/00
US Classification:
345169000
Abstract:
An accelerated dual display enabling a user to dynamically decide which graphics subsystem will run which display on a handheld device. The dual display system has an application processor and an external chip. A crossbar located in the external chip connects the application processor to the external chip. Displays are connected to the crossbar.
Multiplexing Digital Video Out On An Accelerated Graphics Port Interface
US Patent:
6724389, Apr 20, 2004
Filed:
Mar 30, 2001
Appl. No.:
09/823107
Inventors:
Adam H. Wilen - Folsome CA
Marcus Grindstaff - Folsom CA
Aditya Sreenivas - El Dorado Hills CA
Marcus Grindstaff - Folsom CA
Aditya Sreenivas - El Dorado Hills CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 1314
US Classification:
345520, 710100
Abstract:
The present invention is a method and apparatus to map first graphics pins into second graphics pins. A first plurality of data and command pins corresponding to data and command signals in a first graphics mode is mapped into a second plurality of data and command pins corresponding to data and command signals in a second graphics mode. The first and second graphics modes are supported by a first chipset. The second graphics mode is supported by a second chipset. A detector pin strappable to a logic level to indicate an external graphics card is used in the first graphics mode is mapped into a first pin corresponding to a first signal of the second graphics mode. The first signal is ignored by the second chipset during initialization.
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