Mark S Bader, 442312 Westforest Dr, Austin, TX 78704

4972374, Nov 20, 1990

Dec 27, 1989

7/457646

Karl L. Wang - Austin TX
Mark D. Bader - Austin TX

Motorola, Inc. - Schaumburg IL

G11C 706
G11C 514

365205

A memory uses address transition detection to reduce power consumption of the output amplification stage. The output amplification stage, which drives an output driver, has a series of stages which are disabled except when there is an address transition. When there is an address transition all of the stages are quickly enabled except the last stage. The last stage has its output clamped to an invalid state when the other stages are first enabled and then is enabled a predetermined time after the other stages are enabled. The output of the last stage is sensed by a detector. After the last stage has been enabled and is providing valid data, the detector detects that the output of the last stage is valid, and the series of stages are all disabled. The output driver latches the data and provides an output. The output stage is thus disabled and thus not wasting power except during the portion of a cycle when there is actual need for amplification.

4689771, Aug 25, 1987

Mar 3, 1986

6/835679

Karl L. Wang - Austin TX
Mark D. Bader - Austin TX

Motorola, Inc. - Schaumburg IL

G11C 1140

365189

A memory has a read mode in which data is read from a bit line pair selected by a column address and a write mode in which data is written onto a selected bit line pair. The selected bit line pair is coupled to a data line pair via a column decoder in response to a column address. Upon a transition from the write mode to the read mode the column decoder is disabled from coupling the selected data line to the data line pair for the duration of a column disable pulse. The column disable pulse is generated in response to a write transition pulse or a column transition pulse or both. The column transition pulse is generated in response to a change in the column address. The write transition pulse is generated in response to a write to read transition.

5448523, Sep 5, 1995

Sep 15, 1994

8/306564

James C. Lewis - Austin TX
Mark D. Bader - Austin TX

Motorola Inc. - Schaumburg IL

G11C 1500

36518907

A cache TAG RAM (25) includes a TAG array (26), a small signal exclusive OR logic circuit (33, 34), a sense amplifier (36, 37), and another exclusive OR logic circuit (30, 31). A comparison of a stored TAG address to the input address signal is made by the small signal exclusive OR logic circuit (33, 34) to provide a hit signal very quickly. The stored TAG address that is lost during the exclusive OR operation is recovered by performing another exclusive OR on the match information and the input address signal. By using a small signal exclusive OR circuit to perform a comparison early, the hit signal can be generated very quickly.

4751680, Jun 14, 1988

Mar 3, 1986

6/835681

Karl L. Wang - Austin TX
Mark D. Bader - Austin TX
Peter H. Voss - Austin TX

Motorola, Inc. - Schaumburg IL

G11C 700

365203

A memory has a memory cells located at intersections of bit line pairs and word lines. During a write mode of the memory, the bit lines are at a maximum voltage separation. For a read to occur following a write, the bit lines must first be equalized. Because of the extent of the voltage separation during a write, equalizing the bit lines can cause a large peak current drain on the power supply. This peak current is reduced by partially charging the bit lines in response to a write to read transition then bringing the bit lines to the final equalization voltage in response to a transition of the row address. The partial charging is ensured of occurring first in the event that the write to read transition occurs simultaneously with a row address transition to ensure a reduced peak current.

5268863, Dec 7, 1993

Jul 6, 1992

7/909485

Mark D. Bader - Austin TX
Kenneth W. Jones - Austin TX
Karl L. Wang - Austin TX
Ray Chang - Austin TX

Motorola, Inc. - Schaumburg IL

G11C 700

36518901

A memory (20) for performing read cycles and write cycles has memory cells (30) located at intersections of word lines (32) and bit line pairs (34). A write control circuit (44) receives a write enable signal. The logic state of the write enable signal determines whether memory (20) writes data into, or reads data from, memory (20). Memory (20) includes row address decoding for selecting a word line (32). During a write cycle, a control signal generated by write control circuit (44) and single-sided delay circuit (45) is provided to row predecoder (42). The old row address is latched, and a new address is prevented from selecting a new word line (32) until the write enable signal changes state to begin a read cycle. Controlling word line selection with the write enable signal ensures that bit line equalization occurs before the beginning of a read cycle.

5473561, Dec 5, 1995

Sep 15, 1994

8/306565

Kenneth W. Jones - Austin TX
Mark D. Bader - Austin TX
Ketan B. Shah - Round Rock TX

Motorola Inc. - Schaumburg IL

G11C 1500

365 49

A cache TAG RAM (25) includes a reduction circuit (39) for comparing match signals from a plurality of exclusive OR logic circuits (33, 34) and provides a hit signal when all of the TAG address bits of a stored TAG address is the same as input address bits. The reduction circuit (39) provides a miss signal when any one or more of the bits of the stored TAG address is not the same as the corresponding bits of the input address bits. In one embodiment, the reduction circuit (39) uses a plurality of transistors (77, 78) coupled to a conductor (75) for discharging the conductor (75) if one of the exclusive OR logic circuits (33, 34) indicates a miss. In another embodiment, the reduction circuit (39") charges the conductor. The comparison can be made using signals having small signal swing at high speed, and a reference voltage is not needed for the comparison.

5043945, Aug 27, 1991

Sep 5, 1989

7/402733

Mark D. Bader - Austin TX

Motorola, Inc. - Schaumburg IL

G11C 700
G11C 1140

365190

A memory for performing read cycles and write cycles has memory cells located at intersections of word lines and complementary bit line pairs. A row decoder receives a row address and drives a word line in response. In the read cycle, a column decoder decodes a column address to couple selected bit line pairs to global data lines for subsequent output. In the write cycle, write global data lines receive input data signals and couple them to selected bit line pairs for storage in memory cells located at intersections of the selected bit line pairs and enabled word lines. After the write cycle, equalization of bit lines is achieved partly by bit line loads coupled to each bit line, and partly by write data line loads located in the column decoder. Because the write data line loads are coupled to the bit lines after column decoding has taken place, the write data line loads can be shared by several bit line pairs. Thus, layout space is saved due to the sharing, and transistors in the write data line load can be made larger to improve the speed of the bit line equalization.

4764900, Aug 16, 1988

Mar 24, 1986

6/843460

Mark Bader - Austin TX
Karl L. Wang - Austin TX

Motorola, Inc. - Schaumburg IL

G11C 700

365189

In a random access memory a write driver develops a full rail write signal which is coupled to the selected bit line pair via transmission gates. The bit lines are thus driven to full rail. This results in a faster rise time on the bit line which is driven to a logic high. With the faster rise time, the selected cell is written into more quickly with the result of a faster write time for the memory.