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Mark J Botelho, 4759 Pattys Rd, Mansfield, MA 02048

Mark Botelho Phones & Addresses

59 Pattys Rd, Mansfield, MA 02048    508-2382345   

308 Maple St, Mansfield, MA 02048   

1 Hilltop Ln, South Easton, MA 02375   

52 Hurd Ave, Saugus, MA 01906   

Queenstown, MD   

Waltham, MA   

Mentions for Mark J Botelho

Mark Botelho resumes & CV records

Resumes

Mark Botelho Photo 29

Senior Hardware Engineer

Location:
9 Crestfield St, Mattapoisett, MA 02739
Industry:
Computer Hardware
Work:
Viasat Inc.
Senior Hardware Engineer
Emc Jan 1999 - May 2006
Senior Design Engineer
Education:
Northeastern University 1995 - 2000
Skills:
Embedded Systems, Hardware, Debugging, Hardware Architecture, Engineering, Asic, Fpga, System Architecture, Storage, Testing, Perl, C, Linux, Embedded Software, Cross Functional Team Leadership, Cloud Computing, Product Management
Mark Botelho Photo 30

Mark Botelho

Location:
Mansfield, MA
Mark Botelho Photo 31

Mark Botelho

Mark Botelho Photo 32

Mark Botelho

Mark Botelho Photo 33

Mark Botelho

Location:
United States
Mark Botelho Photo 34

Mark Botelho

Location:
Greater Boston Area
Industry:
Financial Services
Mark Botelho Photo 35

Mark Botelho

Publications & IP owners

Us Patents

Data Storage System Having Port Disable Mechanism

US Patent:
7099980, Aug 29, 2006
Filed:
Dec 18, 2003
Appl. No.:
10/740220
Inventors:
Brian D. Magnuson - Somerville MA, US
Mark Botelho - South Easton MA, US
Daniel Castel - Boston MA, US
Assignee:
EMC Corporation - Hopkinton MA
International Classification:
G06F 13/00
G06F 12/00
US Classification:
710301, 711148
Abstract:
A system interface having a backplane adapted to have plugged therein director boards and memory boards. Each one of such director boards includes director board transmit/receive units. Each one of the director board transmit/receive units is associated with a corresponding one of the of memory boards. Each one of the director board transmit/receive units is adapted to be disabled in the absence of the one of the memory boards associated with such one of the director board transmit/receive units. Each one of the memory boards includes memory board transmit/receive units. Each one of the memory board transmit/receive units is associated with a corresponding one of the director boards. Each one of the memory board transmit/receive units is adapted to be disabled to prevent transmit/receive data therethrough in the absence of the one of such director boards associated with such one of the memory board transmit/receive units.

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