BackgroundCheck.run
Search For

Mark Alan Dempsky, 661724 Falmouth Dr, Plano, TX 75025

Mark Dempsky Phones & Addresses

1724 Falmouth Dr, Plano, TX 75025    972-5175262   

Dallas, TX   

Glendale Heights, IL   

Des Plaines, IL   

Villa Park, IL   

1724 Falmouth Dr, Plano, TX 75025    972-7681814   

Social networks

Mark Alan Dempsky

Linkedin

Work

Company: Fujitsu May 2011 Address: Richardson, TX Position: Technical trainer

Education

Degree: BS, EET School / High School: Northern Illinois University 1976 to 1980

Skills

Software Engineering • Programming • Ethernet • Embedded Systems • Rtos • Perl • Project Management • C • Hardware • System Testing • Software Development • Testing • Linux • Tcp/Ip • Debugging • Embedded Software • Unix • Software Project Management • Leadership • Telecommunications • Solaris • Snmp • Voip • Operating Systems • Sdh • Version Control • Threads • V&V • Software Design • Systems Engineering • Integration • Wireless • Uml • Sql • Lte • C++ • Ip • Clearcase • Agile Methodologies • Requirements Analysis • Shell Scripting • Gsm • Xml • Java • System Architecture

Ranks

Certificate: License 418144168894Dtbk

Industries

Computer Software

Mentions for Mark Alan Dempsky

Mark Dempsky resumes & CV records

Resumes

Mark Dempsky Photo 19

Technical Trainer

Location:
Dallas, TX
Industry:
Computer Software
Work:
Fujitsu - Richardson, TX since May 2011
Technical Trainer
Alcatel-Lucent 1985 - 2011
Software Engineer
Education:
Northern Illinois University 1976 - 1980
BS, EET
Skills:
Software Engineering, Programming, Ethernet, Embedded Systems, Rtos, Perl, Project Management, C, Hardware, System Testing, Software Development, Testing, Linux, Tcp/Ip, Debugging, Embedded Software, Unix, Software Project Management, Leadership, Telecommunications, Solaris, Snmp, Voip, Operating Systems, Sdh, Version Control, Threads, V&V, Software Design, Systems Engineering, Integration, Wireless, Uml, Sql, Lte, C++, Ip, Clearcase, Agile Methodologies, Requirements Analysis, Shell Scripting, Gsm, Xml, Java, System Architecture
Certifications:
License 418144168894Dtbk
License 20115X2
License A0Cbbx1
Cisco, License 418144168894Dtbk
Ethernet Academy, License 20115X2
Ethernet Academy, License A0Cbbx1
Cisco Certified Network Professional
Carrier Ethernet Certified Professional 2.0
Carrier Ethernet Certified Professional

Publications & IP owners

Us Patents

Channel Redundancy In A Digital Loop Carrier System

US Patent:
4878048, Oct 31, 1989
Filed:
Aug 10, 1988
Appl. No.:
7/230641
Inventors:
Jeffrey L. Gottesman - Morris Plains NJ
Mark A. Dempsky - Glendale Heights IL
Donald E. Koch - Aurora IL
Dev R. Rattan - Chicago IL
Assignee:
Rockwell International Corporation - El Segundo CA
International Classification:
H04K 100
US Classification:
340825010
Abstract:
A channel redundancy system for use with a central office connected to a remote location. A central office terminal at the central office has a plurality of channel units including at least one spare channel unit. A remote terminal at the remote location also has a plurality of channel units including at least one spare channel unit. The channel units in the remote terminal are correspondingly associated with the channel units in the central office termimal. From a repair service bureau located remote from both the central office and the remote location in a defective channel unit can be identified and replaced by the spare channel unit.

Method For Effecting One Timer Interrupt For Multiple Port Communication

US Patent:
4707782, Nov 17, 1987
Filed:
Sep 7, 1984
Appl. No.:
6/648869
Inventors:
Steve Dumbovic - Elmhurst IL
Mark A. Dempsky - Villa Park IL
Assignee:
Illinois Tool Works Inc. - Chicago IL
International Classification:
G06F 1322
US Classification:
364200
Abstract:
A method for effecting full duplex communications through a plurality of ports of a processing apparatus having one timer. Each output and input signal is expressed as a plurality of bit time intervals. The timer is operated to establish cycles of duration equal to the bit time interval with each of the cycles being divided into sub-bits; designating one of the sub-bits within each of the cycles as a transmitting sub-bit and, upon commencement of the transmitting sub-bit, latching the output pins of appropriate ports at a signal level indicating an output signal bit for transmission at such ports and, upon completion of that latching, interrogating all of the ports for presence of an input signal; upon commencement of sub-bits other than a transmitting sub-bit, interrogating all of the ports for presence of input signals; designating sub-bits of a first cycle during which presence of an input signal is detected as initial sub-bits and identifying sub-bits immediately succeeding initial sub-bits as confirming sub-bits on a port-by-port basis; recognizing input signals detected during confirming sub-bits as true input signals and tagging ports at which true input signals are detected as true input ports; after such tagging, effecting selective interrogation of true input ports in subsequent cycles during sub-bits appearing in a sequential order corresponding to the confirming sub-bits in the first cycle, which selective interrogation of each of the true input ports continues until the input signal at respective true input ports ceases.

NOTICE: You may not use BackgroundCheck or the information it provides to make decisions about employment, credit, housing or any other purpose that would require Fair Credit Reporting Act (FCRA) compliance. BackgroundCheck is not a Consumer Reporting Agency (CRA) as defined by the FCRA and does not provide consumer reports.