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Mark Alan Baur, 5910813 Callanish Park Dr, Austin, TX 78750

Known as:
Mark A Baur Mark N Baur Mark A Bauer
Related to:
Jennifer L Baur 58

Mark Baur Phones & Addresses

10813 Callanish Park Dr, Austin, TX 78750   

3312 Starlight Vis, Round Rock, TX 78664    512-2466287   

Fairfield, OH   

Georgetown, TX   

Poughkeepsie, NY   

Pflugerville, TX   

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Mark Baur resumes & CV records

Resumes

Mark Baur Photo 28

Vice President Engineering - Stb

Location:
Austin, TX
Industry:
Semiconductors
Work:
Ambiq Microcontroller
Director of Digitial Development Maxlinear
Director of Stb Ip and Video Entropic Communications
Vice President Engineering - Stb Trident Microsystems Mar 2010 - Mar 2012
Director of Ip Development Nxp Semiconductors Aug 2008 - Mar 2010
Director of Ip Development - Austin Conexant Aug 2005 - Aug 2008
Director of Verification Conexant 2006 - 2008
Director of Vlsi Develolpment
Education:
University of Cincinnati
Bachelors
Skills:
Set Top Box, Soc, Rtl Design, Semiconductors, Vlsi, Asic, Ic, Fpga, Digital Signal Processors, Embedded Systems, Rtl Coding, Dft, Arm, Verilog, Ip, Functional Verification, Debugging, Ncsim, Eda, Mixed Signal, Static Timing Analysis, Analog, Systemverilog, Silicon Validation
Mark Baur Photo 29

Mark Baur

Mark Baur Photo 30

Mark Baur

Mark Baur Photo 31

Mark Baur

Publications & IP owners

Us Patents

Very Low Power Microcontroller System

US Patent:
2019007, Mar 14, 2019
Filed:
Mar 22, 2018
Appl. No.:
15/933153
Inventors:
- Austin TX, US
Daniel Martin Cermak - Austin TX, US
Eric Jonathan Deal - Austin TX, US
Stephen James Sheafor - Boulder CO, US
Donovan Scott Popps - Austin TX, US
Mark A. Baur - Austin TX, US
International Classification:
G06F 1/32
Abstract:
A microcontroller system includes a processing unit supporting at least one near or sub Vt circuit and a plurality of memory blocks, each memory block connected to a DMA controller and independently power controlled. A power control system uses power gates to power control at least the memory blocks. In some embodiments, a wake-up interrupt controller is connected to the power control system and a voltage regulator system is used to supply voltage to separate power domains, with the voltage regulator systems controlled at least in part by power gates operated by the power control system. A plurality of clocks can be connected to define clock domains associated with separate power domains.

Very Low Power Microcontroller System

US Patent:
2019007, Mar 14, 2019
Filed:
Jun 11, 2018
Appl. No.:
16/005315
Inventors:
- Austin TX, US
Daniel Martin Cermak - Austin TX, US
Eric Jonathan Deal - Austin TX, US
Stephen James Sheafor - Boulder CO, US
Donovan Scott Popps - Austin TX, US
Mark A. Baur - Austin TX, US
International Classification:
G06F 1/32
Abstract:
A microcontroller system includes a processing unit supporting at least one near or sub Vt circuit and a plurality of memory blocks, each memory block connected to a DMA controller and independently power controlled. A power control system uses power gates to power control at least the memory blocks. In some embodiments, a wake-up interrupt controller is connected to the power control system and a voltage regulator system is used to supply voltage to separate power domains, with the voltage regulator systems controlled at least in part by power gates operated by the power control system. A plurality of clocks can be connected to define clock domains associated with separate power domains.

Very Low Power Microcontroller System

US Patent:
2019007, Mar 14, 2019
Filed:
Jun 20, 2018
Appl. No.:
16/013767
Inventors:
- Austin TX, US
Daniel Martin Cermak - Austin TX, US
Eric Jonathan Deal - Austin TX, US
Stephen James Sheafor - Boulder CO, US
Donovan Scott Popps - Austin TX, US
Mark A. Baur - Austin TX, US
International Classification:
G06F 1/32
Abstract:
A microcontroller system includes a processing unit supporting at least one near or sub Vt circuit and a plurality of memory blocks, each memory block connected to a DMA controller and independently power controlled. A power control system uses power gates to power control at least the memory blocks. In some embodiments, a wake-up interrupt controller is connected to the power control system and a voltage regulator system is used to supply voltage to separate power domains, with the voltage regulator systems controlled at least in part by power gates operated by the power control system. A plurality of clocks can be connected to define clock domains associated with separate power domains.

Possible Relatives

Cynthia A Baur  Daniel M Baur  Diane P Baur  Donald T Baur  Ellen H Baur  Eric R Baur  Erwin Baur  Mark W Johnson  Mark E Stamps  Mark Stancil 

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